ISPPAC-CLK5610AV-01T48C Overview
Clock generator is packaged in the way of Tray. Clock PLL is embedded in the 48-LQFP package. The peak reflow temperature (Cel) amounts to 240 to be essentially indestructible. 48 terminations can be found in frequency generators. The supply voltage of 3.3V allows for high efficiency. HSTL, LVCMOS, LVDS, LVPECL, LVTTL, SSTL is designed for clock generator's input. 1 circuits are used to achieve clock PLL's superior flexibility. 400MHz is the maximal value for normal operation. PLL clock is mounted in the way of Surface Mount. The maximal supply voltage (Vsup) reaches 3.6V. The supply voltage (Vsup) should be kept above 3V for normal operation. Clock generators should operate with the voltage supply of 3V~3.6V. The temperature should be set at 0°C~70°C to ensure reliable performance. EHSTL, HSTL, LVCMOS, LVDS, LVPECL, LVTTL, SSTL is designed for clock generator's output. Clock PLL is equipped with 48 pin count. According to the base part number, its related parts can be founded. Clock generator is designed with 48 pins. Clock generator can also be included into Clock Drivers. This clock generator is a member of ispClock™ series. The maximal same edge skew (tskwd) can not be exceeded. This clock generator belongs to the family of 5600. The logic IC PLL clock adopts is PLL BASED CLOCK DRIVER.
ISPPAC-CLK5610AV-01T48C Features
Available in the 48-LQFP
Supply voltage of 3.3V
ISPPAC-CLK5610AV-01T48C Applications
There are a lot of Lattice Semiconductor Corporation
ISPPAC-CLK5610AV-01T48C Clock Generators applications.
- Wireless infrastructure
- Instrument
- Automatic test equipment
- Wide area power system
- Digital circuits
- Wireless base station for LTE, LTE-advanced
- Picocells, femtocells and small cells
- Sampling clocks for ADC and DAC
- 1 Gigabit Ethernet
- 10 Gigabit Ethernet
