FDG1024NZ Description
The dual N-channel logic level enhanced mode field effect transistor is produced by proprietary high cell density DMOS technology. This very high-density process is specially tailored to minimize on-resistance. The device is designed for low-voltage applications as a substitute for bipolar digital transistors and small-signal MOSFET. Because there is no need for bias resistors, this dual-digital FET can replace several different digital transistors with different bias resistance values.
FDG1024NZ Features
Max rDS(on) = 175 mO at VGS = 4.5 V, ID = 1.2 A
Max rDS(on) = 215 mO at VGS = 2.5 V, ID = 1.0 A
Max rDS(on) = 270 mO at VGS = 1.8 V, ID = 0.9 A
Max rDS(on) = 389 mO at VGS = 1.5 V, ID = 0.8 A
HBM ESD protection level >2 kV (Note 3)
Very low level gate drive requirements allowing operation in 1.5 V circuits (VGS(th) < 1 V)
Very small package outline SC70-6
RoHS Compliant
FDG1024NZ Applications
This product is general usage and suitable for many different applications.
