FDG6304P Description
These dual P-channel logic level enhanced mode field effect transistors are produced using proprietary high cell density DMOS technology. This very high-density process is specially tailored to minimize on-resistance. The device is designed for low-voltage applications as a substitute for bipolar digital transistors and small-signal MOSFET.
FDG6304P Features
N-Ch 0.22 A, 25 V,
RDS(ON) = 4.0 |? @ VGS= 4.5 V,
RDS(ON) = 5.0 |? @ VGS= 2.7 V
P-Ch -0.41 A,-25V,
RDS(ON) = 1.1 |? @ VGS= -4.5V,
RDS(ON) = 1.5 |? @ VGS= -2.7V.
Very small package outline SC70-6.
Very low level gate drive requirements allowing direct operation in 3 V circuits (V GS(th) < 1.5 V)
Gate-Source Zener for ESD ruggedness (>6k V Human Body Model).
FDG6304P Applications
This product is general usage and suitable for many different applications.
