NTLUD3A50PZTAG Description
These dual P-channel logic level enhanced mode field effect transistors are produced using on Semiconductor's proprietary high cell density DMOS technology. This very high-density process is specially tailored to minimize state resistance. The device is specially designed for low-voltage applications as a substitute for bipolar digital transistors and small-signal MOSFET.
NTLUD3A50PZTAG Features
? UDFN Package with Exposed Drain Pads for Excellent Thermal
Conduction
? Low RDS(on)
? Low Profile UDFN 2.0x2.0x0.55 mm for Board Space Saving
? These Devices are Pb?Free, Halogen Free/BFR Free and are RoHS
Compliant
NTLUD3A50PZTAG Applications
? High Side Load Switch
? Reverse Current Protection
? Battery Switch
? Optimized for Power Management Applications for Portable
Products, such as Cell Phones, PMP, DSC, GPS, and others
