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LPC55S28JEV98K
NXP USA Inc.
512KB 512K x 8 FLASH ARM® Cortex®-M33 32-Bit Microcontroller LPC55S2x Series 98-VFBGA
SOT-23
LPC55S28JEV98K Datasheet PDF
non-compliant
| Parameter Name | Value |
|---|---|
| Type | Parameter |
| Factory Lead Time | 16 Weeks |
| Mounting Type | Surface Mount |
| Package / Case | 98-VFBGA |
| Operating Temperature | -40°C~105°C TA |
| Series | LPC55S2x |
| Part Status | Active |
| Moisture Sensitivity Level (MSL) | 3 (168 Hours) |
| Oscillator Type | Internal |
| Number of I/O | 64 |
| Speed | 150MHz |
| RAM Size | 256K x 8 |
| Voltage - Supply (Vcc/Vdd) | 1.8V~3.6V |
| Core Processor | ARM® Cortex®-M33 |
| Peripherals | Brown-out Detect/Reset, DMA, I2S, POR, PWM, WDT |
| Program Memory Type | FLASH |
| Core Size | 32-Bit |
| Program Memory Size | 512KB 512K x 8 |
| Connectivity | Flexcomm, I2C, MMC/SD/SDIO, SPI, UART/USART, USB |
| Data Converter | A/D 10x16b |
| RoHS Status | ROHS3 Compliant |
| Quantity | Unit Price | Ext. Price |
| 1 | $6.61000 | $6.61 |
| 500 | $6.5439 | $3271.95 |
| 1000 | $6.4778 | $6477.8 |
| 1500 | $6.4117 | $9617.55 |
| 2000 | $6.3456 | $12691.2 |
| 2500 | $6.2795 | $15698.75 |
The LPC55S28JEV98K is an ARM Cortex-M33-based microcontroller for embedded applications. These devices include a CASPER Crypto/FFT engine, up to 256 KB of on-chip SRAM, up to 512 KB on-chip flash, PRINCE module for on-the-fly flash encryption/decryption, high-speed and full-speed USB host and device interface with the crystal-less operation for full-speed, SD/MMC/SDIO interface, five general-purpose timers, one SCTimer/PWM, one RTC/alarm timer, one 24-bit Multi-Rate Timer (MRT), a Windowed Watchdog Timer (WWDT), nine flexible serial communication peripherals (which can be configured as a USART, SPI, high-speed SPI, I2C, or I2S interface), Programmable Logic Unit (PLU), one 16-bit 1.0 Msamples/sec ADC, comparator, and temperature sensor.
The LPC55S28JEV98K additionally supports secure boot, HASH, AES, RSA, UUID, dynamic encrypt and decrypt, debug authentication, and TBSA compliance to fulfill security requirements.
Secure Boot support:
Uses RSASSA-PKCS1-v1_5 signature of SHA256 digest as cryptographic signature verification.
Supports RSA-2048 bit public keys (2048 bit modulus, 32-bit exponent).
Supports RSA-4096 bit public keys (4096 bit modulus, 32-bit exponent).
Uses x509 certificate format to validate image public keys.
Supports up to four revocable Root of Trust (RoT) or Certificate Authority keys, Root of Trust establishment by storing the SHA-256 hash digest of the hashes of four RoT public keys in protected flash region (PFR).
Supports anti-rollback feature using image key revocation and supports up to 16 Image key certificates revocations using Serial Number field in x509 certificate.
Serial interfaces:
? Flexcomm Interface contains up to nine serial peripherals (Flexcomm Interface 0-7 and Flexcomm Interface 8). Each Flexcomm Interface (except flexcomm 8, which is dedicated for high-speed SPI) can be selected by software to be a USART, SPI, I2C, and I2S interface. Each Flexcomm Interface includes a FIFO that supports USART, SPI, and I2S. A variety of clocking options are available to each Flexcomm Interface, including a shared fractional baud-rate generator, and time-out feature.Flexcomm interfaces 0 to 7 each provide one channel pair of I2S.
I2C-bus interfaces support Fast-mode and Fast-mode Plus with data rates of up to 1Mbit/s and with multiple address recognition and monitor mode. Two sets of true I2C pads also support high-speed Mode (3.4 Mbit/s) as a slave.
USB 2.0 full speed host/device controller with on-chip PHY and dedicated DMA controller supporting crystal-less operation in device mode using software library example in technical note (TN00063).
USB 2.0 high-speed host/device controller with on-chip high-speed PHY
ARM Cortex-M33 core (r0p3):
Running at a CPU frequency of up to 150 MHz
Memory Protection Unit (MPU).
ARM Cortex M33 built-in Nested Vectored Interrupt Controller (NVIC).
Non-maskable Interrupt (NMI) input with a selection of sources.
Serial Wire Debug with eight breakpoints and four watch points. Includes Serial Wire Output for enhanced debug capabilities.
System tick timer.
CASPER Crypto co-processor is provided to enable hardware acceleration for various functions required for certain asymmetric cryptographic algorithms, such as, Elliptic Curve Cryptography (ECC).
On-chip memory:
Up to 512 KB on-chip flash program memory with flash accelerator and 256 byte page erase and write.
Up to 256 KB total SRAM consisting of 32 KB SRAM on Code Bus, 208 KB SRAM on System Bus (192 KB is contiguous), and additional 16 KB USB SRAM on System Bus which can be used by the USB interface or for general purpose use.
Light sensing & controlling devices
Temperature sensing and controlling devices
Fire detection & safety devices
Industrial instrumentation devices
Process control devices
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