FDPC5030SG Description
The device includes two specialized N-channel MOSFET in the dual package. The switch node is connected internally to facilitate the placement and wiring of the synchronous step-down converter. The control of MOSFET (Q1) and synchronous FET (Q2) is designed to provide optimal power efficiency.
FDPC5030SG Features
Q1 N-Channel
Max. RDS(on) = 5.0 m|? at VGS = 10 V, ID = 17 A
Max. RDS(on) = 6.5 m|? at VGS = 4.5 V, ID = 14 A
Q2 N-Channel
Max. RDS(on) = 2.4 m|? at VGS = 10 V, ID = 25 A
Max. RDS(on) = 3.0 m|? at VGS = 4.5 V, ID = 22 A
Low Inductance Packaging Shortens Rise/Fall Times, Resulting in Lower Switching Losses
MOSFET Integration Enables Optimum Layout for Lower Circuit Inductance and Reduced Switch Node Ringing
RoHS Compliant
FDPC5030SG Applications
Computing
Communications
General Purpose Point of Load
