FDG6321C datasheet pdf and Transistors - FETs, MOSFETs - Arrays product details from ON Semiconductor stock available on our website
SOT-23
FDG6321C Datasheet PDF
non-compliant
Technical Specifications
Parameter Name
Value
Type
Parameter
Factory Lead Time
10 Weeks
Lifecycle Status
ACTIVE (Last Updated: 2 days ago)
Contact Plating
Tin
Mount
Surface Mount
Mounting Type
Surface Mount
Package / Case
6-TSSOP, SC-88, SOT-363
Number of Pins
6
Weight
28mg
Transistor Element Material
SILICON
Operating Temperature
-55°C~150°C TJ
Packaging
Tape & Reel (TR)
Published
2017
JESD-609 Code
e3
Pbfree Code
yes
Part Status
Active
Moisture Sensitivity Level (MSL)
1 (Unlimited)
Number of Terminations
6
ECCN Code
EAR99
Resistance
450mOhm
Additional Feature
LOGIC LEVEL COMPATIBLE
Subcategory
Other Transistors
Max Power Dissipation
300mW
Terminal Form
GULL WING
Current Rating
500mA
Number of Elements
2
Element Configuration
Dual
Operating Mode
ENHANCEMENT MODE
Power Dissipation
300mW
FET Type
N and P-Channel
Transistor Application
SWITCHING
Rds On (Max) @ Id, Vgs
450m Ω @ 500mA, 4.5V
Vgs(th) (Max) @ Id
1.5V @ 250μA
Input Capacitance (Ciss) (Max) @ Vds
50pF @ 10V
Current - Continuous Drain (Id) @ 25°C
500mA 410mA
Gate Charge (Qg) (Max) @ Vgs
2.3nC @ 4.5V
Rise Time
8ns
Polarity/Channel Type
N-CHANNEL AND P-CHANNEL
Fall Time (Typ)
8 ns
Turn-Off Delay Time
55 ns
Continuous Drain Current (ID)
500mA
Threshold Voltage
800mV
Gate to Source Voltage (Vgs)
8V
Drain Current-Max (Abs) (ID)
0.5A
Drain to Source Breakdown Voltage
25V
FET Technology
METAL-OXIDE SEMICONDUCTOR
Max Junction Temperature (Tj)
150°C
FET Feature
Logic Level Gate
Height
1.1mm
Radiation Hardening
No
REACH SVHC
No SVHC
RoHS Status
ROHS3 Compliant
Lead Free
Lead Free
In-Stock:15607 items
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Unit Price
Ext. Price
FDG6321C Product Details
FDG6321C Description
On Semiconductor's patented, high cell density DMOS technology is used to create these dual N & P-Channel logic level enhancement mode field effect transistors. Onstate resistance is specifically reduced by this very high density method. This device was created specifically as a low voltage substitute for small signal MOSFETS and bipolar digital transistors. This dual digital FET can replace numerous distinct digital transistors with various bias resistor values because bias resistors are not necessary.
FDG6321C Features
SC70-very 6's compact packaging shape.
low-level gate drive specifications that permit direct
VGS(th) 1.5 V operating in 3 V circuits.
For ESD robustness (>6kV human body model), use a gate-source zener.
FDG6321C Applications
Switching applications
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