FDC6320C Description
These dual Numbp channel logic level enhanced mode field effect transistors are produced using proprietary high cell density DMOS technology. This very high-density process is specially tailored to minimize on-resistance. The device is an improved design, which is especially suitable for low voltage applications as an alternative to bipolar digital transistors in load switching applications. Because there is no need for bias resistors, this dual digital FET can replace multiple digital transistors with different bias resistors.
FDC6320C Features
N-Ch 25 V, 0.22 A, RDS(ON) = 5 |? @ VGS= 2.7 V.
P-Ch 25 V, -0.12 A, RDS(ON) = 13 |? @ VGS= -2.7 V.
Very low level gate drive requirements allowing direct operation in 3 V circuits. VGS(th) < 1.5 V.
Gate-Source Zener for ESD ruggedness. >6kV Human Body Model.
Replace NPN & PNP digital transistors.
FDC6320C Applications
This product is general usage and suitable for many different applications.
