STM8S105K6U6A

STM8S105K6U6A Description

The STM8S105K6U6A access line 8-bit microcontroller provides inbuilt real data EEPROM in addition to 16 to 32 Kbytes of Flash program memory. Devices from this series are referred to as medium-density in the STM8S microcontroller family reference manual (RM0016). The STM8S105K6U6A access range of devices all offers the following advantages: lower system costs, performance and resilience, quick development times, and long product lifespans.

An integrated real data EEPROM with up to 300 k write/erase cycles and a high level of system integration with internal clock oscillators, watchdog, and brown-out reset decrease the system cost.

A 16 MHz CPU clock frequency and improved features such as strong I/O, independent watchdogs (with a separate clock source), and a clock security mechanism guarantee device performance.

Due to application scalability across common family product architecture with comparable pinout, memory map, and modular peripherals, short development cycles are ensured.

The STM8S family's sophisticated core, which is made in cutting-edge technology for applications with 2.95 V to 5.5 V operating supply, ensures the longevity of their products.

A large selection of development tools is available, along with comprehensive documentation.

STM8S105K6U6A Features

Timers

• Advanced control timer: 16-bit, 4 CAPCOM channels, 3 complementary outputs, dead-time insertion and flexible synchronization

• 2x16-bit general purpose timer, with 2+3 CAPCOM channels (IC, OC or PWM)

• 8-bit basic timer with 8-bit prescaler

• Auto wake-up timer

• Window watchdog and independent watchdog timers

Communication interfaces

• UART with clock output for synchronous operation, SmartCard, IrDA, LIN master mode

• SPI interface up to 8 Mbit/s

• I2C interface up to 400 kbit/s

Analog to digital converter (ADC)

• 10-bit, ±1 LSB ADC with up to 10 multiplexed channels, scan mode and analog watchdog

I/Os

• Up to 38 I/Os on a 48-pin package including 16 high sink outputs

• Highly robust I/O design, immune against current injection

Unique ID

• 96-bit unique key for each device

Core

• 16 MHz advanced STM8 core with Harvard architecture and 3-stage pipeline

• Extended instruction set

Memories

• Program memory: up to 32 Kbyte Flash; data retention 20 years at 55 °C after 10 kcycle

• Data memory: up to 1 Kbyte true data EEPROM; endurance 300 kcycle

• RAM: up to 2 Kbyte

Clock, reset and supply management

• 2.95 to 5.5 V operating voltage

• Flexible clock control, 4 master clock sources

– Low power crystal resonator oscillator

– External clock input

– Internal, user-trimmable 16 MHz RC

– Internal low-power 128 kHz RC

• Clock security system with clock monitor

• Power management:

– Low-power modes (wait, active-halt, halt)

– Switch-off peripheral clocks individually

• Permanently active, low-consumption poweron and power-down reset

Interrupt management

• Nested interrupt controller with 32 interrupts

• Up to 37 external interrupts on 6 vectors

STM8S105K6U6A Applications

• Central processing unit STM8

• Single wire interface module (SWIM) and debug module (DM)

• Interrupt controller

• Flash program and data EEPROM memory

• Clock controller

• Power management

• Watchdog timers