STM32L4S9ZIJ6 Description
An ultra-low-power microcontroller family (STM32L4+ Series) based on the powerful Arm? Cortex?-M4 32-bit RISC processor is the STM32L4S9ZIJ6 chip. They run at up to 120 MHz of frequency.
All of the Arm? single-precision data-processing instructions and all data types are supported by the Cortex-M4 core's single-precision floating-point unit (FPU). A memory protection unit (MPU) and a full set of DSP (digital signal processing) instructions are also implemented by the CortexM4 core, which increases the security of the program.
These chips include two OctoSPI Flash memory interfaces, a flexible external memory controller (FSMC) for static memories, two high-speed memories (2 Mbytes of Flash memory and 640 Kbytes of SRAM), a flexible external memory controller (FSMC) for static memories (for devices with packages of 100 pins and more), and a wide range of enhanced I/Os and peripherals connected to two APB buses, two AHB buses, and a 32-bit multi-AHB bus matrix.
The STM32L4S9ZIJ6 device integrates readout protection, write protection, proprietary code readout protection, and a firewall as well as other protection methods for embedded Flash memory and SRAM.
A fast 12-bit ADC (5 Msps) is available, along with two comparators, two operational amplifiers, two DAC channels, an internal voltage reference buffer, a low-power RTC, two general-purpose 32-bit timers, two 16-bit PWM timers for motor control, seven general-purpose 16-bit timers, and two 16-bit low-power timers. Four digital filters are supported by the devices for external sigma delta modulators (DFSDM). Also accessible are up to 24 capacitive sensing channels.
STM32L4S9ZIJ6 Features
RTC with hardware calendar, alarms and calibration
Up to 24 capacitive sensing channels: support touchkey, linear and rotary touch sensors
Advanced graphics features
– Chrom-ART Accelerator (DMA2D) for enhanced graphic content creation
– Chrom-GRC (GFXMMU) allowing up to 20% of graphic resources optimization
– MIPI? DSI Host controller with two DSI lanes running at up to 500 Mbit/s each
– LCD-TFT controller
16x timers: 2 x 16-bit advanced motor-control, 2 x 32-bit and 5 x 16-bit general purpose, 2x16-bit basic, 2x low-power 16-bit timers (available in Stop mode), 2x watchdogs, SysTick timer
Up to 136 fast I/Os, most 5 V-tolerant, up to 14 I/Os with independent supply down to 1.08 V
Memories
– 2-Mbyte Flash, 2 banks read-while-write, proprietary code readout protection
– 640 Kbytes of SRAM including 64 Kbytes with hardware parity check
– External memory interface for static memories supporting SRAM, PSRAM, NOR, NAND and FRAM memories
– 2 x Octo-SPI memory interface
– 1.71 V to 3.6 V power supply
– -40 °C to 85/125 °C temperature range
– Batch acquisition mode (BAM)
– 305 nA in VBAT mode: supply for RTC and 32x32-bit backup registers
– 33 nA Shutdown mode (5 wakeup pins)
– 125 nA Standby mode (5 wakeup pins)
– 420 nA Standby mode with RTC
– 2.8 μA Stop 2 with RTC
– 110 μA/MHz Run mode
– 5 μs wakeup from Stop mode
– Brownout reset (BOR) in all modes except Shutdown
– Interconnect matrix
Core: Arm? 32-bit Cortex?-M4 CPU with FPU, adaptive real-time accelerator (ART Accelerator) allowing 0-wait-state execution from Flash memory, frequency up to 120 MHz, MPU, 150 DMIPS/1.25 DMIPS/MHz (Dhrystone 2.1), and DSP instructions
Performance benchmark
– 1.25 DMIPS/MHz (Drystone 2.1)
– 409.20 CoreMark? (3.41 CoreMark/MHz @120 MHz)
– 233 ULPMark?CP score
– 56.5 ULPMark?PP score
– 4 to 48 MHz crystal oscillator
– 32 kHz crystal oscillator for RTC (LSE)
– Internal 16 MHz factory-trimmed RC (±1%)
– Internal low-power 32 kHz RC (±5%)
– Internal multispeed 100 kHz to 48 MHz oscillator, auto-trimmed by LSE (better than ±0.25 % accuracy)
– Internal 48 MHz with clock recovery
– 3 PLLs for system clock, USB, audio, ADC
STM32L4S9ZIJ6 Applications
