STM32F205RET6TR Description
The STM32F20x family is built around the high-performance Arm? Cortex?-M3 32-bit RISC CPU, which operates at a frequency of up to 120 MHz. The family also includes high-speed integrated memories and a variety of enhanced I/Os and peripherals connected to two APB buses, three AHB buses, and a 32-bit multi-AHB bus matrix (Flash memory up to 1 Mbyte, up to 128 Kbytes of system SRAM, up to 4 Kbytes of backup SRAM).
The devices also have an adaptive real-time memory accelerator (ART AcceleratorTM), which allows for zero wait state performance while running programs from Flash memory at CPU clocks up to 120 MHz. This performance has been verified using the CoreMark? benchmark.
STM32F205RET6TR Features
3 × 12-bit, 0.5 μs ADCs with up to 24 channels and up to 6 MSPS in triple interleaved mode
2 × 12-bit D/A converters
General-purpose DMA: 16-stream controller with centralized FIFOs and burst support
8- to 14-bit parallel camera interface (48 Mbyte/s max.)
CRC calculation unit
96 bit unique ID
Up to 1 Mbyte of Flash memory
512 bytes of OTP memory
Up to 128 + 4 Kbytes of SRAM
Flexible static memory controller that supports Compact Flash, SRAM, PSRAM, NOR and NAND memories
LCD parallel interface, 8080/6800 modes
STM32F205RET6TR Applications
Power Management
Consumer Electronics
Portable Devices
Industrial
