SPEAR300-2 Description
The SPEAR300-2 internal architecture is based on several shared subsystem logic blocks interconnected through a multilayer interconnection matrix. The switch matrix structure allows different subsystem dataflow to be executed in parallel improving the core platform efficiency. High-performance master agents are directly interconnected with the memory controller reducing the memory access latency. The overall memory bandwidth assigned to each master port can be programmed and optimized through an internally efficient weighted round-robin arbitration mechanism.
SPEAR300-2 Features
ARM926EJ-S core up to 333 MHz
High-performance 8-channel DMA
Dynamic power-saving features
Configurable peripheral functions on 102 shared I/Os
32 KB ROM and 56 KB internal SRAM
Integrated real-time clock, watchdog, and system controller
SPEAR300-2 Applications
General purpose NAND Flash or NOR Flash-based devices
Digital photo frames
WiFi or IP phones (low-end or high-end)
ATA PABX systems (with or without I2S)
8-bit or 14-bit camera (with or without LCD)
