ADSP-21060CZ-160 Description
The ADSP-21060CZ-160 SHARC®—Super Harvard Architecture Computer—is a 32-bit signal processing microcomputer offering high DSP performance levels.
The ADSP-21060CZ-160 builds on the ADSP-21000 DSP core to form a complete system-on-a-chip, adding a dual-ported on-chip SRAM and integrated I/O peripherals supported by a dedicated I/O bus.
Fabricated in a high-speed, low-power CMOS process, the ADSP-21060CZ-160 has a 25 ns instruction cycle time and operates at 40 MIPS. With its on-chip
instruction cache, the processor can execute every instruction in a single cycle.
ADSP-21060CZ-160 Features
High-performance signal processor for communications, graphics, and imaging applications
Super Harvard Architecture
- 4 independent buses for dual data fetch, instruction fetch, and nonintrusive I/O
32-bit IEEE floating-point computation units—multiplier, ALU, and shifter
Dual-ported on-chip SRAM and integrated I/O peripherals—a complete system-on-a-chip
Integrated multiprocessing features
ADSP-21060CZ-160 Applications
Automotive
Hybrid, electric & powertrain systems
Industrial
Electronic point of sale (EPOS)
Enterprise systems
Datacenter & enterprise computing
