SI5395D-A11052-GM Overview
Clock generator is packaged in the way of Tray. Clock PLL is embedded in the 64-VFQFN Exposed Pad package. The peak reflow temperature (Cel) amounts to NOT SPECIFIED to be essentially indestructible. LVCMOS is designed for clock generator's input. 1 circuits are used to achieve clock PLL's superior flexibility. 350MHz is the maximal value for normal operation. PLL clock is mounted in the way of Surface Mount. Clock generators should operate with the voltage supply of 1.71V~1.89V 3.14V~3.47V. The temperature should be set at -40°C~85°C TA to ensure reliable performance. CML, HCSL, LVDS, LVPECL, LVCMOS is designed for clock generator's output. This electronic component can be classified into Clock Multiplier, Jitter Attenuator.
SI5395D-A11052-GM Features
Available in the 64-VFQFN Exposed Pad
SI5395D-A11052-GM Applications
There are a lot of Silicon Labs
SI5395D-A11052-GM Clock Generators applications.
- Wireless infrastructure
- Instrument
- Automatic test equipment
- Wide area power system
- Digital circuits
- Wireless base station for LTE, LTE-advanced
- Picocells, femtocells and small cells
- Sampling clocks for ADC and DAC
- 1 Gigabit Ethernet
- 10 Gigabit Ethernet
