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74LVC2G74GD,125

74LVC2G74GD,125

74LVC2G74GD,125

Rochester Electronics, LLC

1.65V~5.5V 200MHz D-Type Flip Flop 40μA 74LVC Series 8-XFDFN

SOT-23

74LVC2G74GD,125 Datasheet PDF

non-compliant

Technical Specifications

Parameter NameValue
TypeParameter
Mounting Type Surface Mount
Package / Case 8-XFDFN
Supplier Device Package 8-XSON (2x3)
Operating Temperature-40°C~125°C TA
PackagingTape & Reel (TR)
Series 74LVC
Part StatusObsolete
Moisture Sensitivity Level (MSL) 1 (Unlimited)
Type D-Type
Voltage - Supply 1.65V~5.5V
Function Set(Preset) and Reset
Output Type Differential
Number of Elements 1
Clock Frequency 200MHz
Current - Quiescent (Iq) 40μA
Current - Output High, Low 32mA 32mA
Number of Bits per Element 1
Max Propagation Delay @ V, Max CL 4.1ns @ 5V, 50pF
Trigger Type Positive Edge
Input Capacitance4pF
RoHS StatusROHS3 Compliant
In-Stock:44908 items

Pricing & Ordering

QuantityUnit PriceExt. Price
1$0.14000$0.14
500$0.1386$69.3
1000$0.1372$137.2
1500$0.1358$203.7
2000$0.1344$268.8
2500$0.133$332.5

74LVC2G74GD,125 Product Details

74LVC2G74GD,125 Overview


In the form of 8-XFDFN, it has been packaged. The Tape & Reel (TR)package contains it. The output it is configured with uses Differential. The trigger it is configured with uses Positive Edge. There is an electric part mounted in the way of Surface Mount. The supply voltage is set to 1.65V~5.5V. In this case, the operating temperature is -40°C~125°C TA. Logic flip flops of this type are classified as D-Type. The FPGA belongs to the 74LVC series. This D flip flop should not have a frequency greater than 200MHz. A total of 1elements are present in it. As a result, it consumes 40μA of quiescent current without being affected by external factors. A JK flip flop with a 4pFfarad input capacitance is used here.

74LVC2G74GD,125 Features


Tape & Reel (TR) package
74LVC series

74LVC2G74GD,125 Applications


There are a lot of Rochester Electronics, LLC 74LVC2G74GD,125 Flip Flops applications.

  • High Performance Logic for test systems
  • Differential Individual
  • Power down protection
  • Divide a clock signal by 2 or 4
  • Event Detectors
  • Matched Rise and Fall
  • Clock pulse
  • Balanced Propagation Delays
  • Safety Clamp
  • Computing

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