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558G-01LF

558G-01LF

558G-01LF

Renesas Electronics America Inc.

1 Circuit 250MHz 2:4 Clock Buffer ICS558-01 ClockBlocks? Series 16-TSSOP (0.173, 4.40mm Width)

SOT-23

558G-01LF Datasheet PDF

non-compliant

Technical Specifications

Parameter NameValue
TypeParameter
Factory Lead Time 12 Weeks
Mounting Type Surface Mount
Package / Case 16-TSSOP (0.173, 4.40mm Width)
Operating Temperature0°C~70°C
PackagingTube
Series ClockBlocks™
Part StatusActive
Moisture Sensitivity Level (MSL) 1 (Unlimited)
Type Fanout Buffer (Distribution), Divider, Multiplexer
Voltage - Supply 2.375V~5.5V
Base Part Number ICS558-01
Output 3-State, CMOS
Number of Circuits 1
Frequency (Max) 250MHz
Input CMOS, PECL
Ratio - Input:Output 2:4
Differential - Input:Output Yes/No
RoHS StatusROHS3 Compliant
In-Stock:532 items

Pricing & Ordering

QuantityUnit PriceExt. Price
1$7.85000$7.85
10$7.06500$70.65
96$6.43698$617.95008
192$5.80901$1115.32992
288$5.33799$1537.34112
576$4.86700$2803.392

558G-01LF Product Details

558G-01LF Overview


The clock divider is packaged in a 16-TSSOP (0.173, 4.40mm Width) case. There is a Tube package attached to it. In normal operation, the maximum value is set to 250MHz. As far as I can tell, it is mounted by Surface Mount. Electrical components classified as Fanout Buffer (Distribution), Divider, Multiplexer are classified as such. When the temperature is set to 0°C~70°C, reliable performance is ensured. In general, it should be able to work with a power source of 2.375V~5.5V volts. There is 3-State, CMOS output from clock driver. This object belongs to the ICS558-01 family. Electronic components of the ClockBlocks? series are included in this package.

558G-01LF Features


The operating temperature of 0°C~70°C degrees

558G-01LF Applications


There are a lot of Renesas Electronics America Inc. 558G-01LF Clock Buffers & Drivers applications.

  • Machine made
  • Window comparator
  • High-speed flip-flop
  • Line receiver and signal recovery
  • Clock signal format conversion
  • Automatic test equipment
  • Clock signal level shifting
  • Data communication
  • DDR4 JEDEC standard RDIMM design
  • Computing

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