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FDMS3600S

FDMS3600S

FDMS3600S

ON Semiconductor

FDMS3600S datasheet pdf and Transistors - FETs, MOSFETs - Arrays product details from ON Semiconductor stock available on our website

SOT-23

FDMS3600S Datasheet PDF

non-compliant

Technical Specifications

Parameter NameValue
TypeParameter
Factory Lead Time 13 Weeks
Lifecycle Status ACTIVE (Last Updated: 2 days ago)
Mount Surface Mount
Number of Pins 8
Weight 171mg
PackagingTape & Reel (TR)
JESD-609 Code e3
Pbfree Code yes
Part StatusActive
Moisture Sensitivity Level (MSL) 1 (Unlimited)
Number of Terminations 7
ECCN Code EAR99
Terminal Finish Tin (Sn)
Max Operating Temperature150°C
Min Operating Temperature -55°C
Subcategory FET General Purpose Power
Max Power Dissipation1W
Terminal Position QUAD
JESD-30 Code R-PQFP-N7
Number of Elements 2
Element ConfigurationDual
Operating ModeENHANCEMENT MODE
Power Dissipation2.5W
Case Connection DRAIN SOURCE
Transistor Application SWITCHING
Rise Time5.3ns
Drain to Source Voltage (Vdss) 25V
Polarity/Channel Type N-CHANNEL
Fall Time (Typ) 3.9 ns
Turn-Off Delay Time 38 ns
Continuous Drain Current (ID) 30A
Gate to Source Voltage (Vgs) 20V
Drain Current-Max (Abs) (ID) 15A
Drain to Source Breakdown Voltage 25V
Input Capacitance1.68nF
FET Technology METAL-OXIDE SEMICONDUCTOR
Drain to Source Resistance 1.6mOhm
Rds On Max 5.6 mΩ
Nominal Vgs 1.8 V
Feedback Cap-Max (Crss) 90 pF
Height 1.05mm
Length 5mm
Width 6mm
Radiation HardeningNo
REACH SVHC No SVHC
RoHS StatusROHS3 Compliant
In-Stock:1029 items

Pricing & Ordering

QuantityUnit PriceExt. Price

FDMS3600S Product Details

FDMS3600S Description


In a twin PQFN packaging, this device has two specialized N-Channel MOSFETs. To make synchronous buck converter placement and routing simple, the switch node has been internally connected. To offer maximum power efficiency, the control MOSFET (Q1) and synchronous SyncFETTM (Q2) have been created.



FDMS3600S Features


  • Maximum RDS(on) at VGS = 10 V, ID = 30 A is 1.6 m.

  • At VGS = 4.5 V, ID = 25 A, the maximum RDS(on) is 2.4 m.

  • Reduced rise/fall periods due to reduced inductance packing reduce switching losses.

  • Optimal designing for lower circuit inductance and less switch node ringing is made possible by MOSFET integration.

  • Conforms to RoHS



FDMS3600S Applications


Notebook PC


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