FDC6301N Description
These dual N-channel logic level enhanced mode field effect transistors are produced using proprietary high cell density DMOS technology. This very high-density process is specially tailored to minimize on-resistance. This device is specially designed for low-voltage applications as a substitute for digital transistors. Because there is no need for bias resistors, these N-channel FET can replace several digital transistors with various bias resistors.
FDC6301N Features
25 V, 0.22 A continuous, 0.5 A Peak
RDS(ON) = 5 |? @ VGS= 2.7 V
RDS(ON) = 4 |? @ VGS= 4.5 V
Very low level gate drive requirements allowing direct operation in 3V circuits. VGS(th) < 1.5V
Gate-Source Zener for ESD ruggedness. >6kV Human Body Model
FDC6301N Applications
This product is general usage and suitable for many different applications.
