SPC5607BF1VLU6R Description
The SPC5607BF1VLU6R is an NXP 32-bit MCU, Power Arch core, 1.5MB Flash, 64MHz, -40/+105degC, Automotive Grade, QFP 176. The most recent development in integrated automotive application controllers is this family of 32-bit system-on-chip (SoC) microcontrollers. It is a member of a growing family of solutions with an automotive focus that is created to handle the upcoming wave of body electronics applications in automobiles.
This automobile controller family's cutting-edge and reasonably priced e200z0h host processor core complies with Power Architecture technology and solely uses the VLE (variable-length encoding) APU (Auxiliary Processor Unit), which improves code density. It features high-performance processing that is tuned for low power consumption and operates at speeds of up to 64 MHz. It makes use of the Power Architecture devices' present development infrastructure and is backed by software drivers, operating systems, and configuration code to help users implement it.
SPC5607BF1VLU6R Features
Up to 10 serial communication interface (LINFlex) modules
Up to 6 enhanced full CAN (FlexCAN) modules with configurable buffers
1 inter-integrated circuit (I2C) interface module
Up to 149 configurable general purpose pins supporting input and output operations (package dependent)
Real-Time Counter (RTC)
Clock source from internal 128 kHz or 16 MHz oscillator supporting autonomous wakeup with 1 ms resolution with maximum timeout of 2 seconds
Optional support for RTC with clock source from external 32 kHz crystal oscillator, supporting wakeup with 1 sec resolution and maximum timeout of 1 hour
Up to 8 periodic interrupt timers (PIT) with 32-bit counter resolution
Nexus development interface (NDI) per IEEE-ISTO 5001-2003 Class Two Plus
Device/board boundary scan testing supported per Joint Test Action Group (JTAG) of IEEE (IEEE 1149.1)
On-chip voltage regulator (VREG) for regulation of input supply for all internal levels
Single issue, 32-bit CPU core complex (e200z0h)
— Compliant with the Power Architecture? technology embedded category
— Enhanced instruction set allowing variable length encoding (VLE) for code size footprint reduction. With the optional encoding of mixed 16-bit and 32-bit instructions, it is possible to achieve significant code size footprint reduction.
Up to 1.5 MB on-chip code flash memory supported with the flash memory controller
64 (4 × 16) KB on-chip data flash memory with ECC
Up to 96 KB on-chip SRAM
Memory protection unit (MPU) with 8 region descriptors and 32-byte region granularity on certain family members (Refer to Table 1 for details.)
Interrupt controller (INTC) capable of handling 204 selectable-priority interrupt sources
Frequency modulated phase-locked loop (FMPLL)
Crossbar switch architecture for concurrent access to peripherals, Flash, or RAM from multiple bus masters
16-channel eDMA controller with multiple transfer request sources using DMA multiplexer
Boot assist module (BAM) supports internal Flash programming via a serial link (CAN or SCI)
Timer supports I/O channels providing a range of 16-bit input capture, output compare, and pulse width modulation functions (eMIOS)
2 analog-to-digital converters (ADC): one 10-bit and one 12-bit
Cross Trigger Unit to enable synchronization of ADC conversions with a timer event from the eMIOS or PIT
Up to 6 serial peripheral interface (DSPI) modules
SPC5607BF1VLU6R Applications
