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SCF5249LAG120

SCF5249LAG120

SCF5249LAG120

NXP USA Inc.

ROMless Coldfire V2 32-Bit Microcontroller MCF524x Series 1.8V 144-LQFP

SOT-23

SCF5249LAG120 Datasheet PDF

non-compliant

Technical Specifications

Parameter NameValue
TypeParameter
Factory Lead Time 10 Weeks
Mounting Type Surface Mount
Package / Case 144-LQFP
Surface MountYES
Operating Temperature0°C~70°C TA
PackagingBulk
Series MCF524x
Published 2001
JESD-609 Code e3
Part StatusNot For New Designs
Moisture Sensitivity Level (MSL) 3 (168 Hours)
Number of Terminations 144
ECCN Code 3A991.A.2
Terminal Finish Matte Tin (Sn)
HTS Code8542.31.00.01
Technology CMOS
Terminal Position QUAD
Terminal FormGULL WING
Peak Reflow Temperature (Cel) 260
Supply Voltage 1.8V
Terminal Pitch0.5mm
Time@Peak Reflow Temperature-Max (s) 40
JESD-30 Code S-PQFP-G144
Qualification StatusNot Qualified
Oscillator TypeExternal
Number of I/O 34
Speed 120MHz
RAM Size 96K x 8
Voltage - Supply (Vcc/Vdd) 3V~3.6V
uPs/uCs/Peripheral ICs Type MICROPROCESSOR, RISC
Core Processor Coldfire V2
Peripherals DMA, I2S, POR, Serial Audio, WDT
Clock Frequency 33.86MHz
Program Memory TypeROMless
Core Size 32-Bit
Connectivity I2C, IDE, Memory Card, SPI, UART/USART
Bit Size 32
Data Converter A/D 4x12b
Address Bus Width24
Boundary Scan YES
Low Power Mode YES
External Data Bus Width 16
Format FIXED POINT
Integrated Cache YES
Length 20mm
Height Seated (Max) 1.6mm
Width 20mm
RoHS StatusROHS3 Compliant
In-Stock:239 items

Pricing & Ordering

QuantityUnit PriceExt. Price
300$22.04000$6612

SCF5249LAG120 Product Details

SCF5249LAG120 Description

The SCF5249 was designed as a system controller/decoder for MP3 music players, especially portable MP3 CD players. The 32-bit ColdFire core with

Enhanced Multiply Accumulate (EMAC) unit provides optimum performance and code density for the combination of control code and signal processing

required for MP3 decode, file management, and system control. Low power features include a hardwired CD ROM decoder, advanced 0.18um CMOS process technology, 1.8V core power supply, and on-chip 96KByte SRAM. MP3 decode requires less than 20MHz CPU bandwidth and runs in on-chip SRAM with external access only for data input and output.



SCF5249LAG120 Features

DMA controller with 4 DMA channels

Integrated Enhanced Multiply-accumulate Unit (EMAC)

8-KByte Direct Mapped Instruction Cache

96-KByte SRAM (A 64K and a 32K bank)

Operates from an external crystal oscillator

Supports 16-bit wide SDRAM memories

Serial Audio Interface which supports IIS and EIAJ audio protocols

Digital audio transmitter and two receivers compliant with IEC958 audio protocol

CD-ROM and CD-ROM XA block decoding and encoding function

Two UARTS

Queued Serial Peripheral Interface (QSPI) (Master Only)

Two timers

IDE and SmartMedia interfaces

Analog/Digital Converter

Flash Memory Card Interface

Two I2C modules

System debug support

General Purpose I/O pins shared with other functions


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