S9S12XS256J0VAA Description
The S9S12XS256J0VAA series retains many of the features of the S12XE series, including error correction codes (ECC) on flash memory, stand-alone data flash modules for code or data storage, frequency modulation locking loops (IPLL) that improve EMC performance, and fast ATD converters. The S12XS series provides 32-bit performance, with all the benefits and efficiency of 16-bit MCU, while retaining the low-cost, power, EMC and code-size efficiency advantages currently enjoyed by Freescale's existing 16-bit S12 and S12X MCU series users. Like other members of the S12X series, the S12XS series runs 16-bit wide access, and all peripherals and memories do not have to wait for state. The S12XS series offers 112-pin LQFP, 80-pin QFP, 64-pin LQFP package options and maintains a high degree of pin compatibility with the S12XE series. In addition to the Ihand O ports available in each module, there are up to 18 Ipicot O ports with interrupt capabilities that allow wake-up from stop or wait mode.
S9S12XS256J0VAA Features
Features of the S12XS Family are listed here. Please see Table D-1 for memory options and Table D-2 for
the peripheral features that are available on the different family members.
? 16-bit CPU12X
— Upward compatible with S12 instruction set with the exception of five Fuzzy instructions
(MEM, WAV, WAVR, REV, REVW) which have been removed
— Enhanced indexed addressing
— Access to large data segments independent of PPAGE
? INT (interrupt module)
— Seven levels of nested interrupts
— Flexible assignment of interrupt sources to each interrupt level.
— External non-maskable high priority interrupt (XIRQ)
— The following inputs can act as Wake-up Interrupts
– IRQ and non-maskable XIRQ
– CAN receive pins
– SCI receive pins
– Depending on the package option up to 20 pins on ports J, H and P configurable as rising or
falling edge sensitive
? MMC (module mapping control)
? DBG (debug module)
— Monitoring of CPU bus with tag-type or force-type breakpoint requests
— 64 x 64-bit circular trace buffer captures change-of-flow or memory access information
? BDM (background debug mode)
? OSC_LCP (oscillator)
— Low power loop control Pierce oscillator utilizing a 4MHz to 16MHz crystal
— Good noise immunity
— Full-swing Pierce option utilizing a 2MHz to 40MHz crystal
— Transconductance sized for optimum start-up margin for typical crystals
? IPLL (Internally filtered, frequency modulated phase-locked-loop clock generation)
— No external components required
— Configurable option to spread spectrum for reduced EMC radiation (frequency modulation)
? CRG (clock and reset generation)
— COP watchdog
— Real time interrupt
— Clock monitor
— Fast wake up from STOP in self clock mode
S9S12XS256J0VAA Applications
fast ATD converters
