S9S12XS128J1CAE Description
The new S12XS family of 16-bit micro controllers is a compatible, reduced version of the S12XE family.These families provide an easy approach to develop common platforms from low-end to high-endapplications, minimizing the redesign of software and hardware.Targeted at generic automotive applications and CAN nodes, some typical examples of these applicationsare: Body Controllers, Occupant Detection, Door Modules, RKE Receivers, Smart Actuators, LightingModules and Smart Junction Boxes amongst many others.The S12XS family retains many of the features of the S12XE family including Error Correction Code(ECC) on Flash memory, a separate Data-Flash Module for code or data storage, a Frequency ModulatedLocked Loop (IPLL) that improves the EMC performance and a fast ATD converter.S12XS family delivers 32-bit performance with all the advantages and efficiencies of a 16-bit MCU whileretaining the low cost, power consumption, EMC and code-size efficiency advantages currently enjoyedby users of Freescale’s existing 16-bit S12 and S12X MCU families. Like members of other S12Xfamilies, the S12XS family runs 16-bit wide accesses without wait states for all peripherals and memories.
S9S12XS128J1CAE Features
Features of the S12XS Family are listed here. Please see Table D-1 for memory options and Table D-2 for
the peripheral features that are available on the different family members.
? 16-bit CPU12X
— Upward compatible with S12 instruction set with the exception of five Fuzzy instructions
(MEM, WAV, WAVR, REV, REVW) which have been removed
— Enhanced indexed addressing
— Access to large data segments independent of PPAGE
? INT (interrupt module)
— Seven levels of nested interrupts
— Flexible assignment of interrupt sources to each interrupt level.
— External non-maskable high priority interrupt (XIRQ)
— The following inputs can act as Wake-up Interrupts
– IRQ and non-maskable XIRQ
– CAN receive pins
– SCI receive pins
– Depending on the package option up to 20 pins on ports J, H and P configurable as rising or
falling edge sensitive
? MMC (module mapping control)
? DBG (debug module)
— Monitoring of CPU bus with tag-type or force-type breakpoint requests
— 64 x 64-bit circular trace buffer captures change-of-flow or memory access information
? BDM (background debug mode)
? OSC_LCP (oscillator)
— Low power loop control Pierce oscillator utilizing a 4MHz to 16MHz crystal
— Good noise immunity
— Full-swing Pierce option utilizing a 2MHz to 40MHz crystal
— Transconductance sized for optimum start-up margin for typical crystals
? IPLL (Internally filtered, frequency modulated phase-locked-loop clock generation)
— No external components required
— Configurable option to spread spectrum for reduced EMC radiation (frequency modulation)
? CRG (clock and reset generation)
— COP watchdog
— Real time interrupt
— Clock monitor
— Fast wake up from STOP in self clock mode
? Memory Options
— 64, 128 and 256 Kbyte Flash
— Flash General Features
– 64 data bits plus 8 syndrome ECC (Error Correction Code) bits allow single bit failure
correction and double fault detection
– Erase sector size 1024 bytes
– Automated program and erase algorithm
– Protection scheme to prevent accidental program or erase
– Security option to prevent unauthorized access
– Sense-amp margin level setting for reads
— 4 and 8 Kbyte Data Flash space
S9S12XS128J1CAE Applications
Operating modes:
? Normal single-chip mode
? Special single-chip mode with active background debug mode
NOTE
This chip family does not support external bus modes.
Low-power modes:
? System stop modes
— Pseudo stop mode
— Full stop mode with fast wake-up option
? System wait mode
