P2020NXE2MHC Description
A link status bit (TBI SR [Link Status]) in the TBI Status Register (SR) represents the current state of the SGMII link. The TBI link status bit should become a b'1 after detecting IDLE sequences if Auto-Negotiation (AN) is disabled, and stay at b'1 as long as valid data is received and the TBI is not reset. After numerous invalid characters are received or the TBI is reset, the TBI link status bit should become a b'0, indicating the link is down. When AN is enabled, the TBI link status bit is not set to b'1 until auto-negotiation is complete (TBI CR [AN DONE]=1), but the same criteria apply as when AN is disabled for the TBI link status bit to be set to b'1.
P2020NXE2MHC Features
? PIC (programmable interrupt controller) that adheres to the OpenPIC standard
? Two DMA controllers with four channels
? Timers, DUART, and two I2C controllers
? A more powerful local bus controller (TBC)
? 16 I/O signals for generic use
? Temperature of the operating junction
? WB-TePBGA II, 689-pin, 31 x 31 mm (wire bond temperature-enhanced plastic BGA)
