MPC8541EVTAPF Description
The MPC8541E integrates a PowerPC? processor core built on Power Architecture? technology with system logic required for networking, telecommunications, and wireless infrastructure applications. The MPC8541E is a member of the PowerQUICC? III family of devices that combine system-level support for industry-standard interfaces with processors that implement the embedded category of the Power Architecture technology. For functional characteristics of the processor, refer to the MPC8555E PowerQUICC? III Integrated Communications Processor Reference Manual.
MPC8541EVTAPF Features
Embedded e500 Book E-compatible core
— High-performance, 32-bit Book E-enhanced core that implements the PowerPC architecture
— Dual-issue superscalar, 7-stage pipeline design
— 32-Kbyte L1 instruction cache and 32-Kbyte L1 data cache with parity protection
— Lockable L1 caches—entire cache or on a per-line basis
— Separate locking for instructions and data
— Single-precision floating-point operations
— Memory management unit specially designed for embedded applications
— Enhanced hardware and software debug support
— Dynamic power management
— Performance monitor facility
