MCF5216CVM66 Description
The processor core is comprised of two separate pipelines that are decoupled by an instruction buffer. Thetwo-stage instruction fetch pipeline (IFP) is responsible for instruction-address generation and instructionfetch. The instruction buffer is a first-in-first-out (FIFO) buffer that holds prefetched instructions awaitingexecution in the operand execution pipeline (OEP). The OEP includes two pipeline stages. The first stagedecodes instructions and selects operands (DSOC); the second stage (AGEX) performs instructionexecution and calculates operand effective addresses, if needed.The V2 core implements the ColdFire instruction set architecture revision A with added support for aseparate user stack pointer register and four new instructions to assist in bit processing. Additionally, theMCF5282 core includes the enhanced multiply-accumulate unit (EMAC) for improved signal processingcapabilities. The EMAC implements a 4-stage execution pipeline, optimized for 32 x 32 bit operations,with support for four 48-bit accumulators. Supported operands include 16- and 32-bit signed and unsignedintegers, signed fractional operands, and a complete set of instructions to process these datatypes. TheEMAC provides superb support for execution of DSP operations within the context of a single processor at a minimal hardware cost.
MCF5216CVM66 Features
A block diagram of the MCF528x and MCF521x is shown in Figure 1-1. The main features are as follows:
? Static Version 2 ColdFire variable-length RISC processor
— Static operation
— On-chip 32-bit address and data path
— Processor core and bus frequency up to 80 MHz
— Sixteen general-purpose 32-bit data and address registers
— ColdFire ISA_A with extensions to support the user stack pointer register, and four new
instructions for improved bit processing
— Enhanced Multiply-Accumulate (EMAC) unit with four 48-bit accumulators to support 32-bit
signal processing algorithms
— Illegal instruction decode that allows for 68K emulation support
? System debug support
— Real-time trace for determining dynamic execution path
— Background debug mode (BDM) for in-circuit debugging
— Real time debug support, with one user-visible hardware breakpoint register (PC and address
with optional data) that can be configured into a 1- or 2-level trigger
? On-chip memories
— 2-Kbyte cache, configurable as instruction-only, data-only, or split I-/D-cache
— 64-Kbyte dual-ported SRAM on CPU internal bus, accessible by core and non-core bus masters
(e.g., DMA, FEC) with standby power supply support
— 512 Kbytes of interleaved Flash memory supporting 2-1-1-1 accesses
(256 Kbytes on the MCF5281 and MCF5214, no Flash on MCF5280)
– This product incorporates SuperFlash? technology licensed from SST.
? Power management
— Fully-static operation with processor sleep and whole chip stop modes
— Very rapid response to interrupts from the low-power sleep mode (wake-up feature)
— Clock enable/disable for each peripheral when not used
? Fast Ethernet Controller (FEC) (not available on the MCF5214 and MCF5216)
— 10BaseT capability, half- or full-duplex
— 100BaseT capability, half- or limited-throughput full-duplex
— On-chip transmit and receive FIFOs
— Built-in dedicated DMA controller
MCF5216CVM66 Applications
? Factory automation & control
– Automated sorting equipment
– CNC control
