MCF51JM128VLK Description
MCF51JM128VLK is a member of the Coldfire family of 32-bit reduced instruction set computing (RISC) microprocessors. This document provides an overview of the MCF51JM128 series, focusing on its highly integrated and diverse feature set. The MCF51JM128 series is based on the V1 Coldfire core, and the processor core runs at speeds up to 50.33 MHz. As part of the Freescale controller Continuum , it is an ideal upgrade based on the MC9S08JM60 series 8-bit microcontroller design.
MCF51JM128VLK Features
? 32-bit Version 1 ColdFire Central Processor Unit (CPU)
— Up to 50.33 MHz at 2.7 V – 5.5 V
— Performance (Dhrystone 2.1):
– 0.94 Dhrystone 2.1 MIPS per MHz when running from internal RAM
– 0.76 Dhrystone 2.1 MIPS per MHz when running from flash
— Implements Instruction Set Revision C (ISA_C)
— Supports up to 30 peripheral interrupt requests and seven software interrupts
? On-chip memory
— Up to 128 KB Flash memory with read/program/erase over full operating voltage and temperature range
— Up to 16 KB static random access memory (RAM)
— Security circuitry to prevent unauthorized access to RAM and flash contents
? Power-saving modes
— Two low-power stop plus wait modes
— Peripheral clock enable register can disable clocks to unused modules, thereby reducing currents; this behavior
allows clocks to remain enabled to specific perhipherals in Stop3 mode
— Very lower power real-time counter for use in run, wait, and stop modes with internal and external clock sources
? Four Clock Source Options
— Oscillator (XOSC) — Loop-control Pierce oscillator; crystal or ceramic resonator range of 31.25 kHz to 38.4 kHz
or 1 MHz to 16 MHz
— FLL/PLL controlled by internal or external reference
— Trimmable internal reference allows 0.2% resolution and 2% deviation
? System protection features
— Watchdog computer operating properly (COP) reset with option to run from dedicated 1 kHz internal clock source
or bus clock
— Low-voltage detection with reset or interrupt; selectable trip points
— Illegal opcode and illegal address detection with programmable reset or exception response
— Flash block protection
? Debug support
— Single-wire Background debug interface
— 4 Program Counters plus two address (optional data) breakpoint registers with programmable 1- or 2-level trigger
Response
MCF51JM128VLK Applications
series 8-bit microcontroller
