MC9S12XHZ512CAG Description
Based around the S12X core, the MC912XHZ family runs 16-bit wide accesses without wait states for all peripherals and memories. The MC912XHZ family also features a new flexible interrupt handler, which allows multilevel nested interrupts. The MC912XHZ family features the performance-boosting XGATE co-processor. The XGATE is programmable in the “C” language and runs at twice the bus frequency of the S12. Its instruction set is optimized for data movement, logic, and bit manipulation instructions. Any peripheral module can be serviced by the XGATE. The MC912XHZ family contains up to 512K bytes of Freescale Semiconductor's industry-leading, full automotive qualified Split-Gate Flash memory, with 4K bytes of additional integrated data EEPROM and up to 32K bytes of static RAM.
MC9S12XHZ512CAG Features
HCS12X Core
— 16-bit HCS12X CPU
– Upward compatible with MC9S12 instruction set
– Interrupt stacking and programmer’s model identical to MC9S12
– Instruction queue
– Enhanced indexed addressing
– Enhanced instruction set
— EBI (external bus interface)
— MMC (module mapping control)
— INT (interrupt controller)
— DBG (debug module to monitor HCS12X CPU and XGATE bus activity)
— BDM (background debug mode)
XGATE (peripheral coprocessor)
— Parallel processing module off loads the CPU by providing high-speed data processing and
transfer
— Data transfer between Flash EEPROM, RAM, peripheral modules, and I/O ports
Memory
– 512K, 384K, 256K byte Flash EEPROM
– 4K byte EEPROM
– 32K, 28K, 16K byte RAM
CRG (clock and reset generator)
— Low noise/low power Pierce oscillator
— PLL
— COP watchdog
— Real-time interrupt
— Clock monitor
— Fast wake-up from stop mode
Analog-to-digital converter
— 16 channels, 10-bit resolution
— External conversion trigger capability
ECT (enhanced capture timer)
— 16-bit main counter with 8-bit Prescaler
— 8 programmable input capture or output compare channels
— Four 8-bit or two 16-bit pulse accumulators
PIT (periodic interrupt timer)
— Four timers with independent time-out periods
— Time-out periods selectable between 1 and 224 bus clock cycles
