MC9S12XEQ512MAA Description
The MC9S12XEQ512MAA is a 16-bit microcontroller that operates at a maximum frequency of 50MHz and is based on an upgraded HCS12X CPU with CISC architecture. The device has 512kB of internal storage, 32kB of internal RAM, 4kB of EEPROM, an 8-channel 12-bit A/D converter, and 59 general-purpose I/O pins. This device has one inter-integrated circuit (IIC) bus module, one multi-scalable controller area network (MSCAN) CAN 2.0 A/B software compliant module, two serial communications interfaces (SCI), and three serial peripheral interface modules.
MC9S12XEQ512MAA Features
Debug module
Background debug mode (BDM)
Memory protection unit (MPU)
Low power loop control pierce oscillator utilizing a 4MHz to 16MHz crystal
Internally filtered, frequency modulated phase-locked-loop clock generation (IPLL)
Clock and reset generation (CRG)
COP watchdog
Real-time interrupt
Clock monitor
Fast wake up from STOP in self-clock mode
Enhanced capture timer (ECT) - 8 x 16-bit channels for input capture or output compare
Standard timer module (TIM) - 8 x 16-bit channels for input capture or output compare
Periodic interrupt timer (PIT)
8 PWM (pulse-width modulator) channels
On-chip voltage regulator - two parallel, linear voltage regulators with a bandgap reference
Upward compatible with MC9S12 instruction set
Enhanced indexed addressing
Access to large data segments independent of PPAGE
Interrupt module (INT)
Module mapping control (MMC)
MC9S12XEQ512MAA Applications
