MC9S12XA256CAA Description
The MC9S12XD series will retain the low cost, power consumption, EMC and code size efficiency advantages currently enjoyed by Freescale's existing 16-bit MC9S12 MCU series users. Based on the enhanced S12 kernel, the MC9S12XD series will provide 2 to 5 times the performance of 25 MHz S12 while maintaining a high degree of pin and code compatibility with S12. The MC9S12XD series introduces a performance improvement XGATE module. The parallel processing module uses the enhanced DMA function to reduce the burden of CPU by providing high-speed data processing and transmission between the peripheral module, RAM, flash EEPROM and Icano ports. In addition to CPU, XGATE provides up to 80 MIPS of performance with access to all peripherals, flash EEPROM, and RAM blocks. The MC9S12XD series consists of standard on-chip peripherals. Includes 512K-byte flash EEPROM, 32K-byte RAM, 4K-byte EEPROM, six asynchronous serial communication interfaces (SCI), three serial peripheral interfaces (SPI), an 8-channel IC/OC enhanced capture timer, an 8-channel 10-bit analog-to-digital converter, a 16-channel 10-bit analog-to-digital converter, an 8-channel pulse width modulator (PWM), five CAN 2.0A and B software compatible modules (MSCAN12), A bus block between two IC and a periodic interrupt timer. The MC9S12XD series has a complete 16-bit data path.
MC9S12XA256CAA Features
? HCS12X Core
— 16-bit HCS12X CPU
– Upward compatible with MC9S12 instruction set
– Interrupt stacking and programmer’s model identical to MC9S12
– Instruction queue
– Enhanced indexed addressing
– Enhanced instruction set
— EBI (external bus interface)
— MMC (module mapping control)
— INT (interrupt controller)
— DBG (debug module to monitor HCS12X CPU and XGATE bus activity)
— BDM (background debug mode)
? XGATE (peripheral coprocessor)
— Parallel processing module off loads the CPU by providing high-speed data processing and
transfer
— Data transfer between Flash EEPROM, RAM, peripheral modules, and I/O ports
? PIT (periodic interrupt timer)
— Four timers with independent time-out periods
— Time-out periods selectable between 1 and 224 bus clock cycles
? CRG (clock and reset generator)
— Low noise/low power Pierce oscillator
— PLL
— COP watchdog
— Real time interrupt
— Clock monitor
— Fast wake-up from stop mode
? Port H & Port J with interrupt functionality
— Digital filtering
— Programmable rising or falling edge trigger
? Memory
— 512, 256 and 128-Kbyte Flash EEPROM
— 4 and 2-Kbyte EEPROM
— 32, 16 and 12-Kbyte RAM
? One 16-channel and one 8-channel ADC (analog-to-digital converter)
MC9S12XA256CAA Applications
Low-power modes:
? System stop modes
— Pseudo stop mode
— Full stop mode
? System wait mode
