LPC55S69JBD100K Description
The NPX LPC55S69JBD100K is an ARM Cortex-M33-based microcontroller for embedded applications including an ARM Cortex-M33 coprocessor, CASPER Crypto/FFT engine, PowerQuad hardware accelerator for DSP functions, up to 320 KB of on-chip SRAM, up to 640 KB on-chip flash, PRINCE module for on-the-fly flash encryption/decryption, high-speed and full-speed USB host and device interface with the crystal-less operation for full-speed, SD/MMC/SDIO interface, five general-purpose timers, one SCTimer/PWM, one RTC/alarm timer, one 24-bit Multi-Rate Timer (MRT), a Windowed Watchdog Timer (WWDT), nine flexible serial communication peripherals (which can be configured as a USART, SPI, high-speed SPI, I2C, or I2S interface), Programmable Logic Unit (PLU), one 16-bit 1.0 Msamples/sec ADC, comparator, and temperature sensor.
LPC55S69JBD100K Features
CASPER Crypto co-processor is provided to enable hardware acceleration for various, functions required for certain asymmetric cryptographic algorithms, such as Elliptic
Curve Cryptography (ECC).
PowerQuad hardware accelerator for (fixed and floating point unit) CMSIS DSP functions with the support of SDK software API faster execution of ARM CMSIS instruction set.
On-chip memory:
-Up to 640 KB on-chip flash program memory with flash accelerator and 512-byte page erase and write.
-Up to 320 KB total SRAM consisting of 32 KB SRAM on Code Bus, 272 KB SRAM on System Bus (272 KB is contiguous), and an additional 16 KB USB SRAM on
System Bus which can be used by the USB interface or for general purpose use.
PRINCE module for real-time encryption of data being written to on-chip flash and decryption of encrypted flash data during reading to allow asset protection, such as securing application code, and enabling the secure flash update.
LPC55S69JBD100K Applications
