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LPC54114J256BD64QL
NXP USA Inc.
256KB 256K x 8 FLASH ARM® Cortex®-M4/M0+ 32-Bit Dual-Core Microcontroller LPC54100 Series 3.3V 64-LQFP
SOT-23
LPC54114J256BD64QL Datasheet PDF
non-compliant
| Parameter Name | Value |
|---|---|
| Type | Parameter |
| Factory Lead Time | 18 Weeks |
| Mounting Type | Surface Mount |
| Package / Case | 64-LQFP |
| Surface Mount | YES |
| Operating Temperature | -40°C~105°C TA |
| Packaging | Tray |
| Series | LPC54100 |
| Published | 2010 |
| JESD-609 Code | e3 |
| Part Status | Active |
| Moisture Sensitivity Level (MSL) | 1 (Unlimited) |
| Number of Terminations | 64 |
| Terminal Finish | Tin (Sn) |
| Terminal Position | QUAD |
| Terminal Form | GULL WING |
| Supply Voltage | 3.3V |
| Terminal Pitch | 0.5mm |
| Pin Count | 64 |
| JESD-30 Code | S-PQFP-G64 |
| Supply Voltage-Max (Vsup) | 3.6V |
| Supply Voltage-Min (Vsup) | 1.62V |
| Oscillator Type | Internal |
| Number of I/O | 50 |
| Speed | 100MHz |
| RAM Size | 192K x 8 |
| Voltage - Supply (Vcc/Vdd) | 1.62V~3.6V |
| uPs/uCs/Peripheral ICs Type | MICROCONTROLLER, RISC |
| Core Processor | ARM® Cortex®-M4/M0+ |
| Peripherals | Brown-out Detect/Reset, DMA, POR, PWM, WDT |
| Clock Frequency | 25MHz |
| Program Memory Type | FLASH |
| Core Size | 32-Bit Dual-Core |
| Program Memory Size | 256KB 256K x 8 |
| Connectivity | I2C, SPI, UART/USART, USB |
| Bit Size | 32 |
| Data Converter | A/D 12x12b |
| Has ADC | YES |
| DMA Channels | YES |
| PWM Channels | YES |
| DAC Channels | NO |
| ROM (words) | 262144 |
| On Chip Program ROM Width | 8 |
| RAM (bytes) | 196608 |
| Length | 10mm |
| Height Seated (Max) | 1.6mm |
| Width | 10mm |
| RoHS Status | ROHS3 Compliant |
| Quantity | Unit Price | Ext. Price |
| 1 | $6.55000 | $6.55 |
| 10 | $5.87900 | $58.79 |
| 25 | $5.55760 | $138.94 |
| 160 | $4.81650 | $770.64 |
| 640 | $4.10020 | $2624.128 |
The LPC5411x are ARM Cortex-M4 based microcontrollers for embedded applications.These devices include an ARM Cortex-M0+ coprocessor, up to 192 KB of on-chip SRAM,up to 256 KB on-chip flash, full-speed USB device interface with Crystal-less operation, aDMIC subsystem with PDM microphone interface and I2S, five general-purpose timers,one SCTimer/PWM, one RTC/alarm timer, one 24-bit Multi-Rate Timer (MRT), aWindowed Watchdog Timer (WWDT), eight flexible serial communication peripherals(each of which can be a USART, SPI, or I2C interface), and one 12-bit 5.0 Msamples/secADC, and a temperature sensor.The ARM Cortex-M4 is a 32-bit core that offers system enhancements such as low powerconsumption, enhanced debug features, and a high level of support block integration. TheARM Cortex-M4 CPU incorporates a 3-stage pipeline, uses a Harvard architecture withseparate local instruction and data buses as well as a third bus for peripherals, andincludes an internal prefetch unit that supports speculative branching. The ARMCortex-M4 supports single-cycle digital signal processing and SIMD instructions. Ahardware floating-point unit is integrated in the core.
Dual processor cores: ARM Cortex-M4 and ARM Cortex-M0+. Both cores operate up
to a maximum frequency of 150 MHz.
ARM Cortex-M4 core (version r0p1):
ARM Cortex-M4 processor, running at a frequency of up to 150 MHz.
Floating Point Unit (FPU) and Memory Protection Unit (MPU).
ARM Cortex-M4 built-in Nested Vectored Interrupt Controller (NVIC).
Non-maskable Interrupt (NMI) input with a selection of sources.
Serial Wire Debug (SWD) with six instruction breakpoints, two literal comparators,
and four watch points. Includes Serial Wire Output for enhanced debug
capabilities.
System tick timer.
ARM Cortex-M0+ core
ARM Cortex-M0+ processor, running at a frequency of up to 150 MHz (uses the
same clock as Cortex-M4) with a single-cycle multiplier and a fast single-cycle I/O
port.
ARM Cortex-M0+ built-in Nested Vectored Interrupt Controller (NVIC).
Non-maskable Interrupt (NMI) input with a selection of sources.
Serial Wire Debug with four breakpoints and two watch points.
System tick timer.
On-chip memory:
Up to 256 KB on-chip flash program memory with flash accelerator and 256 byte
page erase and write.
Up to 192 KB total SRAM consisting of 160 KB contiguous main SRAM and an
additional 32 KB SRAM on the I&D buses.
ROM API support:
Flash In-Application Programming (IAP) and In-System Programming (ISP).
ROM-based USB drivers (HID, CDC, MSC, and DFU). Flash updates via USB is
supported.
Supports booting from valid user code in flash, USART, SPI, and I2C.
Legacy, Single, and Dual image boot.
Serial interfaces:
Flexcomm Interface contains eight serial peripherals. Each can be selected by
software to be a USART, SPI, or I2C interface. Two Flexcomm Interfaces also
include an I2S interface. Each Flexcomm Interface includes a FIFO that supports
USART, SPI, and I2S if supported by that Flexcomm Interface. A variety of clocking
options are available to each Flexcomm Interface and include a shared fractional
baud-rate generator.
2C-bus interfaces support Fast-mode and Fast-mode Plus with data rates of up to
1Mbit/s and with multiple address recognition and monitor mode. Two sets of true
2C pads also support high speed mode (3.4 Mbit/s) as a slave.
USB 2.0 full-speed device controller with on-chip PHY and dedicated DMA
controller supporting crystal-less operation in device mode using software library.
See Technical note TN00031 for more details.
? Printers, and scanners
? Alarm systems, video intercom, and HVAC
? Home audio appliances
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