LPC1758FBD80Y Description
The ARM Cortex-M3 based LPC1759/58/56/54/52/51 microcontrollers for embedded applications have a high level of integration and consume little power. A next-generation core, the ARM Cortex-M3 provides system improvements such improved debug tools and deeper support block integration. The CPU frequencies used by the LPC1758/56/57/54/52/51 are up to 100 MHz. Up to 120 MHz of CPU frequency are supported by the LPC1759. The ARM Cortex-M3 CPU uses a Harvard architecture with a three-stage pipeline, independent local instruction and data buses, and a third bus for peripherals. Additionally, the inbuilt prefetch unit of the ARM Cortex-M3 CPU allows speculative branching. The peripheral complement of the LPC1759/58/56/54/52/51 includes up to 512 kB of flash memory, up to 64 kB of data memory, Ethernet MAC, USB Device/Host/OTG interface, 8-channel general purpose DMA controller, 4 UARTs, 2 CAN channels, 2 SSP controllers, SPI interface, 2 I2C-bus interfaces, 2-input plus 2-output I2S-bus interface, 6 channel 12-bit ADC, 10-bit DAC, motor control PWM, Quadrature Encoder interface, 4 general purpose timers, 6-output general purpose PWM, ultra-low power Real-Time Clock (RTC) with separate battery supply, and up to 52 general purpose I/O pins.
LPC1758FBD80Y Features
ARM Cortex-M3 built-in Nested Vectored Interrupt Controller (NVIC).
Split APB bus allows high throughput with few stalls between the CPU and DMA
In-System Programming (ISP) and In-Application Programming (IAP) via on-chip bootloader software.
Up to 512 kB on-chip flash programming memory. Enhanced flash memory accelerator enables high-speed 120 MHz operation with zero wait states.
ARM Cortex-M3 processor, running at frequencies of up to 100 MHz (LPC1758/56/57/54/52/51) or of up to 120 MHz (LPC1759). A Memory Protection Unit (MPU) supporting eight regions is included.
On-chip SRAM includes:
Up to 32 kB of SRAM on the CPU with local code/data bus for high-performance CPU access.
Two/one 16 kB SRAM blocks with separate access paths for higher throughput. These SRAM blocks may be used for Ethernet (LPC1758 only), USB, and DMA memory, as well as for general purpose CPU instruction and data storage.
Eight channel General Purpose DMA controller (GPDMA) on the AHB multilayer matrix that can be used with the SSP, I2S-bus, UART, the Analog-to-Digital and Digital-to-Analog converter peripherals, timer match signals, and for memory-to-memory transfers.
Multilayer AHB matrix interconnect provides a separate bus for each AHB master. AHB masters include the CPU, General Purpose DMA controller, Ethernet MAC (LPC1758 only), and the USB interface. This interconnect provides communication with no arbitration delays.
LPC1758FBD80Y Applications
Automotive
Personal electronics
Communications equipment
