S9S12XF384J2MLMR Description
The S9S12XF384J2MLMR is a MCU based around an enhanced S12X core from the MC9S12XF-Family.
S9S12XF384J2MLMR Features
— Upward compatible with MC9S12 instruction set with the exception of five Fuzzy instructions
(MEM, WAV, WAVR, REV, REVW) which have been removed.
— Enhanced indexed addressing
— Additional (superset) instructions to improve 32-bit calculations and semaphore handling
— Access large data segments independent of PPAGE
— Eight levels of nested interrupt
— Flexible assignment of interrupt sources to each interrupt level
— One non-maskable high priority interrupt (XIRQ)
— Wake-up Interrupt Inputs
— 4 address regions definable per active program task
— Address range granularity as low as 256-bytes
— Protection Attributes
S9S12XF384J2MLMR Applications
