MXD1818XR22+T Overview
There are 3 mounting terminals on the voltage supervisor, each of which has a different function. There is a Tape & Reel (TR)-packaging method applied to IC management. In this PMIC, you can find 1 functions for your reference. There are 1 channels on this power managment ic that can be found in a series. Please find attached SC-70, SOT-323 functions for your reference in this IC power. There are many benefits that this IC power shares with other Simple Reset/Power-On Reset products as well. There is a specification for the peak reflow temperature of the package to be 260. When 3.6V is applied to the power ic, it conducts. In a 1 supply voltage, the PMIC chip conducts. The mount is attached to Surface Mount. This power ic can be sub-categorized as Power Management Circuits. Taking into account all of the pins, this power management has a total of 3. Pin count of the power management is 3. In order for this PMIC to work correctly, the minimum supply voltage (Vsup) should be greater than 1V. It is recommended that the maximum supply voltage (Vsup) in this IC power be no more than 5.5V volts. Power management' mounting is recommended to be done with the Surface Mount type of mounting. It is recommended to set the supervisor's temperature to this range: -40°C~105°C TA. During normal operation, this power managment ic can generate Open Drain, Bidirectional of output voltage. As far as the supply current of the power management is concerned, it is 9μA. You can always use MXD1818, the base supervisor number, to search for similar PMICs of the manufacturer.
MXD1818XR22+T Features
Simple Reset/Power-On Reset type
Minimum supply voltage of 1V
9μA operating supply current
MXD1818XR22+T Applications
There are a lot of Maxim Integrated MXD1818XR22+T Voltage Supervisors applications.
- Microprocessor system
- Cloud computing
- DVR
- Data storage applications
- Important electronics for automotive protection
- Utility meter
- Urban rail transit weak current power monitoring
- Battery cars
- Detection of phase imbalance
- FPGA design
