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CY37128P84-125JI

CY37128P84-125JI

CY37128P84-125JI

Cypress Semiconductor

1.27mm PMIC 84 Pin 125MHz 5V PLCC

SOT-23

CY37128P84-125JI Datasheet PDF

non-compliant

Technical Specifications

Parameter NameValue
TypeParameter
Mount Surface Mount
Package / Case PLCC
Number of Pins 84
JESD-609 Code e0
Moisture Sensitivity Level (MSL) 3 (168 Hours)
Number of Terminations 84
Terminal Finish Tin/Lead (Sn/Pb)
Max Operating Temperature85°C
Min Operating Temperature -40°C
Terminal Position QUAD
Terminal FormJ BEND
Peak Reflow Temperature (Cel) 220
Supply Voltage 5V
Terminal Pitch1.27mm
Frequency 125MHz
Time@Peak Reflow Temperature-Max (s) 30
Pin Count84
Operating Supply Voltage5V
Temperature GradeINDUSTRIAL
Max Supply Voltage5.5V
Min Supply Voltage4.5V
Number of I/O 69
Memory TypeEEPROM
Propagation Delay10 ns
Turn On Delay Time10 ns
Frequency (Max) 125MHz
Organization 1 DEDICATED INPUTS, 69 I/O
Programmable Logic TypeEE PLD
Number of Logic Blocks (LABs) 8
Speed Grade 125
Output FunctionMACROCELL
Number of Macro Cells 128
JTAG BST YES
Number of Dedicated Inputs 1
In-System Programmable YES
Length 29.3116mm
Width 29.3116mm
Radiation HardeningNo
RoHS StatusRoHS Compliant
In-Stock:3407 items

CY37128P84-125JI Product Details

CY37128P84-125JI Overview


128 macrocells exist, which are cells in a mobile phone network that are primarily composed of high-power towers, antennas, or masts.A PLCC package contains the item.This device has 69 I/O ports programmed into it.It is programmed that device terminations will be 84 .The terminal position of this electrical component is QUAD.A voltage of 5V is used as the power supply for this device.Chips are programmed with 84 pins.If high efficiency is to be achieved, the supply voltage should be maintained at 5V.Data storage is performed using EEPROM.In this case, Surface Mount is used to mount the electronic component.The 84 pins are designed into the board.A voltage of 5.5V is the maximum supply voltage for this device.A minimum supply voltage of 4.5V is required for this device to operate.There is a maximum frequency of 125MHz.In order to operate, the temperature should be higher than -40°C.A temperature below 85°C should be used as the operating temperature.The logic block consists of 8 l logic blocks (LABs).To detect input signals, there are 1 dedicated inputs.The maximum frequency should not exceed 125MHz.There is a type of programmable logic called EE PLD.

CY37128P84-125JI Features


PLCC package
69 I/Os
84 pin count
84 pins
8 logic blocks (LABs)


CY37128P84-125JI Applications


There are a lot of Cypress Semiconductor
CY37128P84-125JI CPLDs applications.


  • Address decoders
  • Custom state machines
  • Digital systems
  • Portable digital devices
  • Handheld digital devices
  • Battery operated portable devices
  • Complex programmable logic devices
  • Digital designs
  • Field programmable gate
  • Address decoding

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