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CY37064P44-125JC

CY37064P44-125JC

CY37064P44-125JC

Cypress Semiconductor

1.27mm PMIC 44 Pin 5V PLCC

SOT-23

CY37064P44-125JC Datasheet PDF

non-compliant

Technical Specifications

Parameter NameValue
TypeParameter
Package / Case PLCC
Surface MountYES
Number of Pins 44
JESD-609 Code e0
Moisture Sensitivity Level (MSL) 3 (168 Hours)
Number of Terminations 44
Terminal Finish Tin/Lead (Sn/Pb)
Max Operating Temperature70°C
Min Operating Temperature 0°C
Subcategory Programmable Logic Devices
Technology CMOS
Terminal Position QUAD
Terminal FormJ BEND
Peak Reflow Temperature (Cel) 225
Supply Voltage 5V
Terminal Pitch1.27mm
Time@Peak Reflow Temperature-Max (s) 30
Pin Count44
Qualification StatusNot Qualified
Operating Supply Voltage5V
Temperature GradeCOMMERCIAL
Number of I/O 37
Memory TypeEEPROM
Propagation Delay10 ns
Turn On Delay Time10 ns
Frequency (Max) 125MHz
Organization 1 DEDICATED INPUTS, 37 I/O
Programmable Logic TypeEE PLD
Number of Logic Blocks (LABs) 4
Speed Grade 125
Output FunctionMACROCELL
Number of Macro Cells 64
JTAG BST YES
Number of Dedicated Inputs 1
In-System Programmable YES
Length 16.6116mm
Width 16.6116mm
RoHS StatusRoHS Compliant
In-Stock:1607 items

CY37064P44-125JC Product Details

CY37064P44-125JC Overview


The mobile phone network has 64 macro cells, which are cells that provide radio coverage from high-power cell sites (towers, antennas, or masts).In the PLCC package, you will find it.In this case, there are 37 I/Os programmed.44 terminations are programmed into the device.This electrical component has a terminal position of QUAD.An electrical supply voltage of 5V is used to power it.The part belongs to Programmable Logic Devices family.A chip with 44 pins is programmed.In order to achieve high efficiency, the supply voltage should be maintained at 5V.In this case, EEPROM will be used to store the data.The device has a pinout of 44.Operating temperatures should be higher than 0°C.Ideally, the operating temperature should be below 70°C.There are 4 logic blocks (LABs) that make up its basic building block.To detect the status of input signals, there are 1 dedicated inputs.It should be below 125MHz at the maximal frequency.Programmable logic types are divided into EE PLD.

CY37064P44-125JC Features


PLCC package
37 I/Os
44 pin count
44 pins
4 logic blocks (LABs)


CY37064P44-125JC Applications


There are a lot of Cypress Semiconductor
CY37064P44-125JC CPLDs applications.


  • I/O expansion
  • Discrete logic functions
  • Bootloaders for FPGAs
  • Address decoders
  • Custom state machines
  • Digital systems
  • Portable digital devices
  • Handheld digital devices
  • Battery operated portable devices
  • Complex programmable logic devices

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