EPM7128ELC84-20 Description
The EPM7128ELC84-20 high-density, high-performance PLDs are based on Altera’s second-generation MAX architecture. Fabricated with advanced CMOS technology, the EEPROM-based MAX 7000 family provides 600 to 5,000 usable gates, ISP, pin-to-pin delays as fast as 5 ns, and counter speeds of up to 175.4 MHz. The EPM7128ELC84-20 has several enhanced features: additional global clocking, additional output enable controls, enhanced interconnect resources, fast input registers, and a programmable slew rate.
EPM7128ELC84-20 Features
High-performance, EEPROM-based programmable logic devices(PLDs) based on second-generation MAX® architecture
5.0-V in-system programmability (ISP) through the built-in IEEE Std. 1149.1 Joint Test Action Group (JTAG) interface available in MAX 7000S devices – ISP circuitry compatible with IEEE Std. 1532
Includes 5.0-V MAX 7000 devices and 5.0-V ISP-based MAX 7000S devices
Built-in JTAG boundary-scan test (BST) circuitry in MAX7000S devices with 128 or more macrocells
EPM7128ELC84-20 Applications
Communications equipment
Broadband fixed line access
Enterprise systems
Enterprise projectors
Personal electronics
Portable electronics
