5M80ZT100C5N Description
MAX V devices contain a two-dimensional row- and column-based architecture to implement custom logic. Row and column interconnect provide signal
interconnects between the logic array blocks (LABs). Each LAB in the logic array contains 10 logic elements (LEs). An LE is a small unit of logic that provides
an efficient implementation of user logic functions. LABs are grouped into rows and columns across the device. The MultiTrack interconnect provides fast granular timing delays between LABs.
The fast routing between LEs provides minimum timing delay for added logic levels versus globally routed interconnect structures.
5M80ZT100C5N Features
Low-cost, low-power, and non-volatile CPLD architecture
Instant-on (0.5 ms or less) configuration time
Standby current as low as 25 µA and fast power-down/reset operation
Fast propagation delay and clock-to-output times
Internal oscillator
Single 1.8-V external supply for device core
Four global clocks with two clocks available per logic array block (LAB)
5M80ZT100C5N Applications
Communications equipment
Wired networking
Enterprise systems
Enterprise projectors
Personal electronics
Portable electronics
