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AD9642BCPZ-250

AD9642BCPZ-250

AD9642BCPZ-250

Hotenda

14 Bit 0.5mm Tin ADC AD9642 1.8V 32-WFQFN Exposed Pad, CSP

SOT-23

AD9642BCPZ-250 Datasheet PDF

non-compliant

Technical Specifications

Parameter NameValue
TypeParameter
Factory Lead Time 8 Weeks
Lifecycle Status PRODUCTION (Last Updated: 1 month ago)
Contact PlatingTin
Mounting Type Surface Mount
Package / Case 32-WFQFN Exposed Pad, CSP
Surface MountYES
Number of Pins 32
Operating Temperature-40°C~85°C
PackagingTray
JESD-609 Code e3
Pbfree Code no
Part StatusActive
Moisture Sensitivity Level (MSL) 3 (168 Hours)
Number of Terminations 32
Subcategory Analog to Digital Converters
Max Power Dissipation360mW
Technology CMOS
Terminal Position QUAD
Terminal FormNO LEAD
Peak Reflow Temperature (Cel) 260
Number of Functions 1
Supply Voltage 1.8V
Terminal Pitch0.5mm
Time@Peak Reflow Temperature-Max (s) 30
Base Part Number AD9642
Pin Count32
Qualification StatusNot Qualified
Operating Supply Voltage1.8V
Configuration S/H-ADC
Number of Channels 1
Interface LVDS
Max Supply Voltage1.9V
Min Supply Voltage1.7V
Number of Bits 14
Input Type Differential
Architecture Pipelined
Max Input Voltage 1.75V
Converter Type ADC, FLASH METHOD
Supply Type Single
Reference TypeInternal
Data InterfaceLVDS - Parallel
Resolution 1.75 B
Sampling Rate250 Msps
Voltage - Supply, Analog 1.7V~1.9V
Voltage - Supply, Digital 1.7V~1.9V
Number of Analog In Channels 1
Sampling Rate (Per Second) 250M
Output Bit Code OFFSET BINARY, 2'S COMPLEMENT BINARY, GRAY CODE
Integral Nonlinearity (INL) 2.5 LSB
Input Capacitance2.5pF
Ratio - S/H:ADC 1:1
Output FormatSERIAL
Signal to Noise Ratio (SNR) 72.5 dB
Differential Nonlinearity 0.6 LSB
Conversion Time-Max 0.004μs
Height Seated (Max) 0.8mm
Length 5mm
Width 5mm
REACH SVHC No SVHC
RoHS StatusROHS3 Compliant
Lead Free Contains Lead
In-Stock:85 items

Pricing & Ordering

QuantityUnit PriceExt. Price
1$111.60000$111.6
10$105.84400$1058.44

AD9642BCPZ-250 Product Details

LMK04832NKDT Description


The LMK04832NKDT is an ultra-high-performance clock conditioner with JEDEC JESD204B support and is also pin compatible with the LMK0482x family of devices. The 14 clock outputs from PLL2 can be configured to drive seven JESD204B converters or other logic devices using device and SYSREF clocks. SYSREF can be provided using both DC and AC coupling. Not limited to JESD204B applications, each of the 14 outputs can be individually configured as high-performance outputs for traditional clocking systems.



LMK04832NKDT Features


Maximum Clock Output Frequency: 3255 MHz

Multi-Mode: Dual PLL, Single PLL, and Clock Distribution

1-1023 CLKout Divider

1-8191 SYSREF Divider

25-ps Step Analog Delay for SYSREF Clocks

Digital Delay and Dynamic Digital Delay for Device Clock and SYSREF



LMK04832NKDT Applications


Test and Measurement

RADAR

Microwave Backhaul

Data Converter Clocking


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