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EPM5128JC

EPM5128JC

EPM5128JC

Altera

5V 1.27mm PMIC 5V

SOT-23

EPM5128JC Datasheet PDF

non-compliant

Technical Specifications

Parameter NameValue
TypeParameter
Surface MountYES
JESD-609 Code e0
Pbfree Code no
Number of Terminations 68
ECCN Code EAR99
Terminal Finish Tin/Lead (Sn/Pb)
Additional FeatureLABS INTERCONNECTED BY PIA; 8 LABS; 128 MACROCELLS; 1 EXTERNAL CLOCK; SHARED INPUT/CLOCK
HTS Code8542.39.00.01
Subcategory Programmable Logic Devices
Technology CMOS
Terminal Position QUAD
Terminal FormJ BEND
Peak Reflow Temperature (Cel) 220
Supply Voltage 5V
Terminal Pitch1.27mm
Time@Peak Reflow Temperature-Max (s) 30
Pin Count68
JESD-30 Code S-CQCC-J68
Qualification StatusNot Qualified
Operating Temperature (Max) 70°C
Supply Voltage-Max (Vsup) 5.25V
Power Supplies5V
Temperature GradeCOMMERCIAL
Supply Voltage-Min (Vsup) 4.75V
Number of I/O 52
Clock Frequency 40MHz
Propagation Delay55 ns
Organization 7 DEDICATED INPUTS, 52 I/O
Programmable Logic TypeUV PLD
Output FunctionMACROCELL
Number of Macro Cells 128
JTAG BST NO
Number of Dedicated Inputs 7
In-System Programmable NO
Length 24.13mm
Height Seated (Max) 5.08mm
Width 24.13mm
RoHS StatusNon-RoHS Compliant
In-Stock:4783 items

EPM5128JC Product Details

EPM5128JC Overview


A mobile phone network consists of 128macro cells, which are radio coverage cells served by a high-power cell site (tower, antenna or mast).There are 52 I/Os programmed in it.The device is programmed with 68 terminations.As the terminal position of this electrical part is QUAD, it serves as an important access point for passengers and freight.Power is provided by a supply voltage of 5V volts.It is included in Programmable Logic Devices.The chip is programmed with 68 pins.When using this device, LABS INTERCONNECTED BY PIA; 8 LABS; 128 MACROCELLS; 1 EXTERNAL CLOCK; SHARED INPUT/CLOCK can also be found.The system runs on a power supply of 5V watts.In this case, the maximum supply voltage (Vsup) reaches 5.25V.It has 7 dedicated inputs for detecting input signals.It is recommended that the supply voltage (Vsup) be greater than 4.75V.The clock frequency should not exceed 40MHz.Types of programmable logic are divided into UV PLD.It is recommended that the operating temperature be kept below 70°C.

EPM5128JC Features


52 I/Os
68 pin count
5V power supplies


EPM5128JC Applications


There are a lot of Altera
EPM5128JC CPLDs applications.


  • Voltage level translation
  • Timing control
  • Interface bridging
  • I/O expansion
  • Discrete logic functions
  • Bootloaders for FPGAs
  • Address decoders
  • Custom state machines
  • Digital systems
  • Portable digital devices

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