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EP1810JC-45

EP1810JC-45

EP1810JC-45

Altera

5.08mm mm FPGAs 1.27mm mm 68

SOT-23

EP1810JC-45 Datasheet PDF

non-compliant

Technical Specifications

Parameter NameValue
TypeParameter
Surface MountYES
JESD-609 Code e0
Pbfree Code no
Number of Terminations 68
ECCN Code 3A001.A.7
Terminal Finish Tin/Lead (Sn/Pb)
Additional FeatureMACROCELLS INTERCONNECTED BY GLOBAL AND/OR LOCAL BUS; 48 MACROCELLS; 4 EXTERNAL CLOCKS
HTS Code8542.39.00.01
Subcategory Programmable Logic Devices
Technology CMOS
Terminal Position QUAD
Terminal FormJ BEND
Peak Reflow Temperature (Cel) 220
Supply Voltage 5V
Terminal Pitch1.27mm
Time@Peak Reflow Temperature-Max (s) 30
Pin Count68
JESD-30 Code S-CQCC-J68
Qualification StatusNot Qualified
Operating Temperature (Max) 70°C
Supply Voltage-Max (Vsup) 5.25V
Power Supplies5V
Temperature GradeCOMMERCIAL
Supply Voltage-Min (Vsup) 4.75V
Number of I/O 48
Clock Frequency 22.2MHz
Propagation Delay50 ns
Organization 12 DEDICATED INPUTS, 48 I/O
Programmable Logic TypeUV PLD
Output FunctionMACROCELL
Number of Macro Cells 48
JTAG BST NO
Number of Dedicated Inputs 12
In-System Programmable NO
Length 24.13mm
Height Seated (Max) 5.08mm
Width 24.13mm
RoHS StatusNon-RoHS Compliant
In-Stock:4921 items

EP1810JC-45 Product Details

EP1810JC-45 Overview


An FPGA of this type is made up of UV PLD gates. The device has 48 I/O ports for more coherent data transfer. In order to operate fpga chips, a voltage supply of 5V volts is required. FPGA parts like this belong to the Programmable Logic Devices family. 68 terminations are present in total. There is a 5V power supply that is required to operate it. With a total of 68 pins, it is equipped with a high level of security. It usually uses a 22.2MHz crystal. Addfpga semiconductorionally, fpga semiconductor has a characteristic called MACROCELLS INTERCONNECTED BY GLOBAL AND/OR LOCAL BUS; 48 MACROCELLS; 4 EXTERNAL CLOCKS that gives fpga semiconductor fpga semiconductors uniqueness. To determine the status of the input signals, 12 dedicated inputs are available in the system. For this FPGA to function properly, the supply voltage must be greater than 4.75V. There are 48 macro cells which make up this CPLD and they serve as the main components of the device. A maximum temperature of 70°C degrees Celsius should not be exceeded during operation.

EP1810JC-45 Features


48 I/Os


EP1810JC-45 Applications


There are a lot of Altera
EP1810JC-45 FPGAs applications.


  • Software-defined radio
  • Random logic
  • ASIC prototyping
  • Medical imaging
  • Computer hardware emulation
  • Integrating multiple SPLDs
  • Voice recognition
  • Cryptography
  • Filtering and communication encoding
  • Aerospace and Defense

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