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EP4CE40F29C7N

EP4CE40F29C7N

EP4CE40F29C7N

Intel

2.4mm mm FPGAs Cyclone? IV E Series 780-BGA 1mm mm 780

SOT-23

EP4CE40F29C7N Datasheet

non-compliant

In-Stock: 4809 items
Specifications
Name Value
Type Parameter
Factory Lead Time 8 Weeks
Mounting Type Surface Mount
Package / Case 780-BGA
Surface Mount YES
Operating Temperature 0°C~85°C TJ
Packaging Tray
Series Cyclone® IV E
JESD-609 Code e1
Part Status Active
Moisture Sensitivity Level (MSL) 3 (168 Hours)
Number of Terminations 780
ECCN Code 3A001.A.7.A
Terminal Finish Tin/Silver/Copper (Sn/Ag/Cu)
HTS Code 8542.39.00.01
Subcategory Field Programmable Gate Arrays
Voltage - Supply 1.15V~1.25V
Terminal Position BOTTOM
Terminal Form BALL
Peak Reflow Temperature (Cel) 245
Supply Voltage 1.2V
Terminal Pitch 1mm
[email protected] Reflow Temperature-Max (s) 40
Base Part Number EP4CE40
JESD-30 Code S-PBGA-B780
Number of Outputs 535
Qualification Status Not Qualified
Power Supplies 1.21.2/3.32.5V
Number of I/O 532
Clock Frequency 472.5MHz
Number of Inputs 535
Programmable Logic Type FIELD PROGRAMMABLE GATE ARRAY
Number of Logic Elements/Cells 39600
Total RAM Bits 1161216
Number of LABs/CLBs 2475
Height Seated (Max) 2.4mm
Length 29mm
Width 29mm
RoHS Status RoHS Compliant
Pricing & Ordering
Quantity Unit Price Ext. Price
1 $97.16000 $97.16
EP4CE40F29C7N Product Details

EP4CE40F29C7N Description


The EP4CE40F29C7N is Altera's new Cyclone® IV FPGA device that extends the Cyclone FPGA series leadership in providing the market’s lowest-cost, lowest-power FPGAs, now with a transceiver variant.



EP4CE40F29C7N Features


  • Cyclone IV E—lowest power, high functionality with the lowest cost

  • Cyclone IV GX—most insufficient power and lowest price FPGAs with 3.125 Gbps transceivers

  • 6K to 150K logic elements

  • Up to 6.3 Mb of embedded memory

  • Up to 360 18 × 18 multipliers for DSP processing-intensive applications

  • Protocol bridging applications for under 1.5 W total power

  • Data rates up to 3.125 Gbps

  • 8B/10B encoder/decoder

  • 8-bit or 10-bit physical media attachment (PMA) to physical coding sublayer (PCS) interface

  • Byte serializer/deserializer (SERDES)

  • Word aligner

  • Rate matching FIFO

  • TX bit slipper for Common Public Radio Interface (CPRI)

  • Electrical idle

  • Dynamic channel reconfiguration allows you to change data rates and protocols on-the-fly

  • Static equalization and pre-emphasis for superior signal integrity

  • 150 mW per channel power consumption

  • Flexible clocking structure to support multiple protocols in a single transceiver block



EP4CE40F29C7N Applications


  • Industrial


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