CY2545C005

CY2545
CY2547

Document #: 001-13196 Rev. *A

Page 7 of 15

Figure 3.  Data Transfer Sequence on the Serial Bus

Figure 4.  Data Frame Architecture

Figure 5.  Data Valid and Data Transition Periods

SCL

START

Condition

SDA

STOP

Data may 

Address or 
Acknowledge
Valid

be changed

Condition

SDA

 Write

Start Signal

Device 
Address

7-bit

R/W = 0

1 Bit

8-bit

Register

Address

Slave

1 Bit

ACK

Slave

1 Bit

ACK

8-bit

Register

Data

Stop Signal

Multiple 
Contiguous 
Registers

Slave

1 Bit

ACK

8-bit

Register
Data

(XXH)

(XXH)

(XXH+1)

Slave

1 Bit

ACK

8-bit

Register
Data
(XXH+2)

Slave

1 Bit

ACK

8-bit

Register
Data

(FFH)

Slave

1 Bit

ACK

8-bit

Register
Data
(00H)

Slave

1 Bit

ACK

Slave

1 Bit

ACK

SDA

 Read

Start Signal

Device 
Address

7-bit

R/W = 1

1 Bit

8-bit

Register

Data

Slave

1 Bit

ACK

Slave

1 Bit

ACK

Stop Signal

SDA

 Read

Start Signal

Device 
Address

7-bit

R/W = 0

1 Bit

8-bit

Register

Address

Slave

1 Bit

ACK

Slave

1 Bit

ACK

7-bit

Device

 

Stop Signal

Multiple 
Contiguous 
Registers

Master

1 Bit

ACK

8-bit

Register
Data

Master

1 Bit

ACK

(XXH)

(XXH)

Master

1 Bit

ACK

8-bit

Register
Data
(XXH+1)

Master

1 Bit

ACK

8-bit

Register
Data

(FFH)

Master

1 Bit

ACK

8-bit

Register
Data
(00H)

Master

1 Bit

ACK

Master

1 Bit

ACK

Current
Address
Read

Address
+R/W=1

Repeated
Start bit

SDA

SCL

Data Valid

Transition

 to next Bit

CLK

LOW

CLK

HIGH

VIH

VIL

t

SU

t

DH

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CY2545C005 Information:
Part No.
CY2545C005

RFQ

Description
TSBU
File Size
372387 bytes
Page Size
612 x 792 pts (letter)
All Pages
15
Manufacturer
Cypress Semiconductor
Homepage
http://www.cypress.com/
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