CY2545C005

CY2545
CY2547

Document #: 001-13196 Rev. *A

Page 6 of 15

Serial I

2

C Programming Interface Protocol 

and Timing

To enhance the flexibility and function of the clock synthesizer, a
two signal serial interface is provided. Through the Serial Data
Interface, various device functions, such as individual clock
output buffers, are individually enabled or disabled. The registers
associated with the Serial Data Interface initialize to their default
setting upon power up and therefore, use of this interface is
optional. Clock device register changes are normally made at
system initialization, if any are required. 

The CY2545 and CY2547 use a 2-wire serial interface SDA and
SCL that operates up to 400 kbits/s in read or write mode. The
SDA and SCL timing and data transfer sequence is shown in

Figure 3

. The basic write serial format is: 

Start Bit; 7-bit Device Address (DA); R/W Bit; Slave Clock
Acknowledge (ACK); 8-bit Memory Address (MA); ACK; 8-bit
Data; ACK; 8-bit Data in MA+1 if desired; ACK; 8-bit Data in
MA+2; ACK; etc. until STOP Bit. The basic serial format is illus-
trated in 

Figure 4

.

Device Address

The device serial interface address is 69H. The device address
is combined with a read/write bit as the LSB and is sent after
each start bit.

Data Valid

Data is valid when the clock is HIGH, and is only transitioned
when the clock is LOW, as illustrated in 

Figure 5

.

Data Frame

A start and stop sequence indicates every new data frame, as
illustrated in 

Figure 6

.

Start Sequence - The start frame is indicated by SDA going LOW
when SCL is HIGH. Every time a start signal is supplied, the next
8-bit data must be the device address (seven bits) and a R/W bit,
followed by register address (eight bits) and register data (eight
bits).

Stop Sequence - The stop frame is indicated by SDA going HIGH
when SCL is HIGH. A stop frame frees the bus to go to another
part on the same bus or to another random register address.

Acknowledge Pulse

During write mode the CY2545/CY2547 responds with an
acknowledge pulse after every eight bits. Do this by pulling the
SDA line LOW during the N*9

th

 clock cycle as illustrated in

Figure 7

 (N = the number of bytes transmitted). During read

mode, the master generates the acknowledge pulse after
reading the data packet.

Write Operations

Writing Individual Bytes 

A valid write operation must have a full 8-bit register address
after the device address word from the master, which is followed
by an acknowledge bit from the slave (ack = 0/LOW). The next

eight bits must contain the data word intended for storage. After
the data word is received, the slave responds with another
acknowledge bit (ack = 0/LOW), and the master must end the
write sequence with a STOP condition. 

Writing Multiple Bytes

To write multiple bytes at a time, the master does not end the
write sequence with a STOP condition; instead, the master
sends multiple contiguous bytes of data to be stored. After each
byte, the slave responds with an acknowledge bit, the same as
after the first byte, and accepts data until the STOP condition
responds to the acknowledge bit. When receiving multiple bytes,
the CY2545 and CY2547 internally increment the register
address.

Read Operations

Read operations are initiated the same way as write operations
except that the R/W bit of the slave address is set to ‘1’ (HIGH).
There are three basic read operations: current address read,
random read, and sequential read.

Current Address Read

The CY2545 and CY2547 have an onboard address counter that
retains 1 more than the address of the last word access. If the
last word written or read was word ‘n’, then a current address
read operation returns the value stored in location ‘n+1’. When
the CY2545/CY2547 receive the slave address with the R/W bit
set to a ‘1’, the CY2545/CY2547 issue an acknowledge and
transmit the 8-bit word. The master device does not
acknowledge the transfer, but generates a STOP condition,
which causes the CY2545/CY2547 to stop transmission.

Random Read

Through random read operations, the master may access any
memory location. To perform this type of read operation, first the
word address must be set. This is done by sending the address
to the CY2545/CY2547 as part of a write operation. After sending
the word address, the master generates a START condition
following the acknowledge. This terminates the write operation
before any data is stored in the address, but not before the
internal address pointer is set. Next, the master reissues the
control byte with the R/W byte set to ‘1’. The CY2545/CY2547
then issue an acknowledge and transmit the 8-bit word. The
master device does not acknowledge the transfer, but generates
a STOP condition, which causes the CY2545/CY2547 to stop
transmission.

Sequential Read

Sequential read operations follow the same process as random
reads except that the master issues an acknowledge instead of
a STOP condition after transmitting the first 8-bit data word. This
action increments the internal address pointer, and subsequently
output of the next 8-bit data word. By continuing to issue
acknowledges instead of STOP conditions, the master serially
reads the entire contents of the slave device memory. When the
internal address pointer points to the FFH register, after the next
increment, the pointer points to the 00H register.

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CY2545C005 Information:
Part No.
CY2545C005

RFQ

Description
TSBU
File Size
372387 bytes
Page Size
612 x 792 pts (letter)
All Pages
15
Manufacturer
Cypress Semiconductor
Homepage
http://www.cypress.com/
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