UCC5681PW24



                 

              



SLUS441A – MARCH 1999 – REVISED AUGUST 2000

5

POST OFFICE BOX 655303 

 DALLAS, TEXAS 75265

APPLICATION INFORMATION (continued)

In LVD mode, the regulated voltage is switched to 1.25 V and a resistor network is presented to each line pair
that provides common-mode impedance of 150 

 and differential impedance of 105 

. The lines in each

differential pair are biased so that when not driven, Line(n)+ and Line(n)– are driven 56 mV below and above
the common-mode bias voltage (1.25 V) respectively.

In SE/HVD mode, all the terminating resistors are switched off the bus. The 1.25-V and 1.3-V (DIFSENS)
regulators are left on.

When the disconnect input (DISCNCT) is low, the terminating resistors are switched off the bus and both voltage
regulators are turned off to save power. The mode change filter/delay function is still active and the LVD pin (in
the 28-pin package) continues to indicate the correct bus mode.

The UCC5681 operates down to a TRMPWR voltage of 2.7 V. This accommodates a 3.3-V system with
allowance for supply tolerance (

±

10%), a unidirectional fusing device, and cable drop. The UCC3916 is

recommended in place of a fuse and diode implementation, as its lower voltage drop provides additional voltage
margin for the system.

Layout is important in all SCSI implementations and critical in SPI-3 systems, which have stringent requirements
on both the absolute value of capacitance on differential signal lines and the balancing of capacitance between
paired lines and from pair to pair.

Feedthroughs, through-hole connections, and etch lengths need to be carefully balanced. Standard multilayer
power and ground plane spacing adds about 1 pF to each plane. Each feed-through will add 2.5 pF to 3.5 pF.
Enlarging the clearance holes on both power and ground planes reduces capacitance. Opening up the power
and ground planes under a through-hole connector reduces added capacitance in those applications.
Capacitance is also affected by components in close proximity on both sides of the board.

maximum capacitance

SCSI Class

Trace to GND: 

REQ, ACK, DATA, Parity,

P_CRCA

Trace to Trace: 

REQ, ACK, DATA, Parity,

P_CRCA

Trace to GND:

Other signals

Trace to Trace:

Other Signals

Ultra1

25 pF

N/A

25 pF

N/A

Ultra2

20 pF

10 pF

25 pF

13 pF

Ultra3/Ultra160

15 pF

8 pF

25 pF

13 pF

Ultra320

13 pF

6.5 pF

21 pF (est.)

10 pF (est.)

TI terminators are designed with very tightly controlled capacitance on their signal lines. Between the positive
and negative lines in a differential pair the difference is typically no more than 0.1 pF, and only 0.3 pF between
pairs.

Multi-layer boards need to adhere to the 120-

 impedance standard, including the connector and feedthroughs.

Bus traces are normally run on the outer layers of the board with 4-mil etch and 4-mil spacing between the two
lines in each differential pair, and a minimum of 8-mil spacing to adjacent pairs to minimize crosstalk. Microstrip
technology is too low in impedance and should not be used—it is designed for 50 

 rather than 120-

 differential

systems.

Decoupling capacitors should be installed as close as possible to the following input pins of the UCC5681:

TRMPWR: 4.7-

µ

F capacitor to ground, 0.01-

µ

F capacitor to ground (high-frequency, low ESR)

REG: 4.7-

µ

F capacitor to ground, 0.01-

µ

F capacitor to ground (high-frequency, low ESR)

 

UCC5681PW24 Information:
Part No.
UCC5681PW24

RFQ

Description
UCC5681PW24
File Size
210905 bytes
Page Size
612 x 792 pts (letter)
All Pages
9
Manufacturer
Texas Instruments
Homepage
http://www.ti.com/
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