M24256-BWMN6TP

Instructions

M24256-BW M24256-BR M24256-BF M24256-DR M24256-DF

18/39

DocID6757 Rev 32

5.1.6 Minimizing 

Write 

delays by polling on ACK

The maximum Write time (t

w

) is shown in AC characteristics tables in 

Section 8: DC and AC 

parameters

, but the typical time is shorter. To make use of this, a polling sequence can be 

used by the bus master. 

The sequence, as shown in 

Figure 9

, is:

Initial condition: a Write cycle is in progress.

Step 1: the bus master issues a Start condition followed by a device select code (the 
first byte of the new instruction).

Step 2: if the device is busy with the internal Write cycle, no Ack will be returned and 
the bus master goes back to Step 1. If the device has terminated the internal Write 
cycle, it responds with an Ack, indicating that the device is ready to receive the second 
part of the instruction (the first byte of this instruction having been sent during Step 1).

Figure 9. Write cycle polling flowchart using ACK

1. The seven most significant bits of the Device Select code of a Random Read (bottom right box in the 

figure) must be identical to the seven most significant bits of the Device Select code of the Write (polling 

instruction in the figure).

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M24256-BWMN6TP Information:
Part No.
M24256-BWMN6TP

RFQ

Description
IC EEPROM 256KBIT 1MHZ 8SO
File Size
715127 bytes
Page Size
595 x 842 pts (A4)
All Pages
39
Manufacturer
STMicroelectronics
Homepage
http://www.st.com/web/en/home.html
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