M24256-BWMN6TP

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M24256-BW M24256-BR M24256-BF M24256-DR M24256-DF

Instructions

38

5.1.3 Write 

Identification Page (M24256-D only)

The Identification Page (64 bytes) is an additional page which can be written and (later) 
permanently locked in Read-only mode. It is written by issuing the Write Identification Page 
instruction. This instruction uses the same protocol and format as Page Write (into memory 
array), except for the following differences:

Device type identifier = 1011b

MSB address bits A15/A6 are don't care except for address bit A10 which must be ‘0’. 
LSB address bits A5/A0 define the byte address inside the Identification page.

If the Identification page is locked, the data bytes transferred during the Write Identification 
Page instruction are not acknowledged (NoAck).

5.1.4 Lock 

Identification Page (M24256-D only)

The Lock Identification Page instruction (Lock ID) permanently locks the Identification page 
in Read-only mode. The Lock ID instruction is similar to Byte Write (into memory array) with 
the following specific conditions:

Device type identifier = 1011b

Address bit A10 must be ‘1’; all other address bits are don't care

The data byte must be equal to the binary value xxxx xx1x, where x is don't care

5.1.5 

ECC (Error Correction Code) and Write cycling 

The Error Correction Code (ECC) is an internal logic function which is transparent for the 
I

2

C communication protocol.

The ECC logic is implemented on each group of four EEPROM bytes

(1)

. Inside a group, if a 

single bit out of the four bytes happens to be erroneous during a Read operation, the ECC 
detects this bit and replaces it with the correct value. The read reliability is therefore much 
improved.

Even if the ECC function is performed on groups of four bytes, a single byte can be 
written/cycled independently. In this case, the ECC function also writes/cycles the three 
other bytes located in the same group

(1)

. As a consequence, the maximum cycling budget is 

defined at group level and the cycling can be distributed over the 4 bytes of the group: the 
sum of the cycles seen by byte0, byte1, byte2 and byte3 of the same group must remain 
below the maximum value defined 

Table 11: Cycling performance by groups of four bytes

.

1. A group of four bytes is located at addresses [4*N, 4*N+1, 4*N+2, 4*N+3], where N is an integer.

M24256-BWMN6TP Information:
Part No.
M24256-BWMN6TP

RFQ

Description
IC EEPROM 256KBIT 1MHZ 8SO
File Size
715127 bytes
Page Size
595 x 842 pts (A4)
All Pages
39
Manufacturer
STMicroelectronics
Homepage
http://www.st.com/web/en/home.html
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