Quad-channel RF-sampling analog front end with 14-bit 9GSPS DAC and 3GSPS ADC

By Texas Instruments


The AFE76xx is a family of high performance, quad/dual channel, 14-bit, integrated RF sampling analog front ends (AFEs) with 9 GSPS DACs and 3 GSPS ADCs, capable of synthesizing and digitizing wideband signals. High dynamic range allows the AFE76xx to generate and digitize 3G/4G signals for wireless base stations. In TDD mode, the receiver channel can be configured to dynamically switching between traffic receiver (TDD RX) status and wideband feedback receiver (TDD FB) status to assist DPD (Digital Pre-Distortion) of the Power Amplifier (PA) on the transmitter path.

The AFE76xx family has integrated DSA on the receiver channels and also supports DSA equivalent functionality on the transmitter channels. Each receiver channel has one analog RF peak power detector and various digital power detectors to assist AGC control for receiver channels, and two RF overload detectors for device reliability protection. The AFE76xx family has 8 of JESD204B compatible SerDes transceivers running up to 15 Gbps. The devices have up to two DUCs per TX channel and two DDCs per RX channel, with multiple interpolation/decimation rates and digital quadrature modulators/demodulators with independent, frequency flexible NCOs. The devices support more than 1000 MHz (800 MHz as 4T4R) RF signal bandwidth in single-band mode, and up to 800 MHz (300 MHz as 4T4R) RF signal bandwidth per band in dual-band mode. A low jitter PLL/VCO simplifies the sampling clock generation by allowing use of a lower frequency reference clock.

Features

14-Bit Resolution
Sample Rate:
DAC: 9 GSPS
ADC: 3 GSPS
RF Frequency Range: Up to 5.2 GHz
Maximum RF Signal Bandwidth
Quad-Channel Mode (4T4R): 800 MHz (single-band); 300 MHz (dual-band)
Dual-Channel Mode (2T2R): 1200 MHz (TX)/1000 MHz (RX) (single-band); 800MHz(dual-band)
On-Chip Dual Selectable DSAs per RX Channel
Integrated TX DSA Functionality

Digital:

Dual Band Digital Up-Converters (DUCs)
Dual Band Digital Down-Converters (DDCs)
32-Bit NCOs for DUCs/DDCs
Interpolation Ratio: 6x, 8x, 9x, 12x, 16x, 18x, 24x, 36x
Decimation Ratio: /2, /3, /4, /6, /8, /9, /12, /16, /18, /24, /32
RX/FB Dynamic Switching for TDD

Interface:

8 SerDes Transceivers up to 15Gbps
16-Bit and 12-Bit JESD204B Transport Layer Formatting with 8b/10b Encoding
Subclass 1 Multi-Device Synchronization

Clock:

Internal PLL/VCO to Generate DAC and ADC Clocks
Package: 17mm x 17mm FC BGA, 0.8mm Pitch
Power Supplies: 1.85 V, 1.15 V, 1.0 V, –1.8 V
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