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Wireless Architectures for Data Acquisition in Industrial Automation

This article looks at the different options for capturing data for wireless distribution to enable industrial automation applications. It looks at the different levels of integration for the data capture, and the interfaces to the different wireless technologies that are used for connecting sensors and other equipment. It covers the Microchip MRF49XA transceiver in the unlicensed ISM bands below 900 Hz and the Silicon Labs EM351 for 2.4 GHz applications.

System-on-chip (SoC) devices are becoming increasingly popular for wireless data acquisition designs in industrial automation. A transceiver needs a microcontroller to handle the protocol stack and packetization of the incoming data. Integrating the controller alongside the radio front end reduces the footprint, cost and complexity of the design. The choice of frequency band and protocol depends on the data bandwidth requirements, which in turn is dependent on the sensor architecture and the data acquisition system being used.

However, for lower data rate, cost sensitive applications in lower frequency bands, there is still a place for a separate transceiver that can be easily integrated to a low cost controller, matched to the requirements of the data converter and sensor sub-system.

Wireless systems are used to link sensors around the factory floor to a central monitoring point. These wireless sensor networks (WSN) provide vital data, from the status of a process to the health of a piece of machinery. This helps optimize the performance of the industrial process and flag problems with equipment to allow for replacement before it fails, avoiding costly down time.

Integrated system-on-chip devices such as the Silicon Labs EM351 use the I²C interface, which is a common output from an analog-to-digital converter (ADC). This, along with the SPI interface, can dramatically simplify the design of the node, providing a simple two or four wire interface to the data converter. The choice of converter will be determined by the output protocol to ensure they are well matched in performance – from a lower data rate 868 MHz ISM band with an 8-bit controller to a 2.4 GHz ZigBee node with a 32-bit processor.

The data acquisition stage can use a number of different conversion architectures, depending on how many sensors it has to service, their sampling rate, and the accuracy and frequency of the measurements.

Industrial data acquisition applications may also need a low-power implementation. Being able to place a sensor node exactly where it is needed, using battery power for the wireless node and data capture, can enhance the controllability of the industrial process, so the power consumption of the wireless node and the data converter can be a key design requirement. This is even more important when using energy harvesting as a source of power, using the thermal or vibrational energy from the industrial environment to power the sensor, data converters, and wireless link. This uses rechargeable batteries but eliminates the need to re-charge or replace batteries regularly.

Fortunately, for a wireless node in an industrial application, the latency and bandwidth of the converter is not a critical issue – data flows from the sensor to the wireless node for transmission and processing, rather than being used in a local feedback loop from the sensor to an actuator where the real time performance is more critical. Again, this has an impact on the choice of data converter architecture that is used.

While a wireless sensor network is a communications application, data converter architectures optimized for communications may not be appropriate. Data converters for audio and data transmission applications use the sigma delta architecture (see below) and are optimized for constant streams of data with particular bandwidth limits. This may not match a sensor application where data is not constantly sampled, so a successive approximation device may be more appropriate.

The successive approximation architecture is suitable for 8-bit to 18-bit resolution and sampling rates up to several MHz, which matches well with converting data for a wireless node. The output of the converter is through a standard serial interface such as I²C or SPI, feeding the system data to the microprocessor in the wireless node with a relatively simple link. Unfortunately, the input of these devices does not necessarily match the output of the sensor, often requiring an amplifier as the interface to the sensors. This can increase the power and complexity of the design and can increase the vulnerability to external electrical noise in an industrial environment, requiring additional filtering at 50 or 60 Hz.

Successive approximation

At the heart of the SAR architecture is an input sample-and-hold (SHA) block. This keeps the signal constant during the conversion cycle as the analog data feeds through to the comparator. The advantage of this architecture is that the data feeds through the converter in a simple, linear path, so the data corresponding to that specific sample is available at the end of the conversion time. By avoiding pipeline delay and latency, the SAR can be used in single-shot, burst-mode, and multiplexed applications, such as a bank of sensors, may take a sample every few seconds for monitoring applications and feed the results to the wireless node.

Figure 1: The successive approximation (SAR) data converter architecture.

Because of this lack of pipeline delay, it is relatively simple to add a multiplexed front end to the SAR converter. This has led to the development of complete data-acquisition system on a single chip, adding in other functions such as automatic calibration.

A SAR-based converter may be well suited to a low-power wireless application where the sensor data is read infrequently. A single sample can be converted and transmitted, and then the whole sensor node is shut down until the next sample is required. With a long duty cycle, the energy consumption can be dramatically reduced.

Sigma-Delta converters

The other main candidate for data conversion in industrial wireless applications is the sigma delta (∑Δ) ADC, but these operate is a substantially different way. They are best used for applications requiring higher resolution from 16 to 24 bits and sampling at a few hundred hertz, and are more suited to streaming applications. As a result, the higher data rates may require a higher performance wireless network node such as ZigBee at 2.4 GHz.

However, the ∑Δ architecture has a key advantage for industrial automation, as a programmable-gain amplifier (PGA) can be added to the front of the device to allow small output voltages of sensors to be captured directly. This can reduce the complexity and cost of industrial automation designs.

Another advantage of the architecture for industrial applications is that the averaging of the samples gives good rejection of 50 Hz and 60 Hz power-line frequencies, filtering out the electrical noise that can cause spurious signals.

Figure 2: A second order sigma delta (∑Δ) modulator.

The heart of the ∑Δ converter is a 1-bit analog to digital block. This acts as a comparator that feeds into a 1-bit DAC acting as a switch. The ratio of the 1s in the output stream provides the output value, determined by integrating the stream over the sample time. Using one integrator provides a good linear sample output, and additional integration blocks are used to get higher resolution. This can be seen in Figure 2, with a second integrator boosting the performance of the signal chain by reducing the noise and increasing the resolution.

The noise advantage comes from the architecture acting as a low-pass filter for the signal, and a high-pass filter for the quantization noise. The filter is a key part of the architecture, but introduces a pipeline delay. This is a disadvantage using multiplexed front ends and means more careful design is required. When using a multiplexed front end to combine several sensor inputs into one converter, the latency means the digital filter must settle before the output data is valid, which can take several clock cycles. This is important to take into account when interfacing the output of the converter to the microcontroller in the wireless node.

The ∑Δ converter architecture also dominates voice band and audio applications. A major benefit of the high oversampling rate inherent in the architecture is that they simplify the input antialiasing filter for the ADC and the output filter for the DAC. In addition, the ease of adding digital functions to a CMOS-based converter makes features such as digital-filter programmability practical with only small increases in overall die area, power, and cost.

Digital cellular systems use higher resolution oversampled linear ∑Δ ADCs and DACs as the typical signal to noise (SNR) requirements are 60 dB to 70 dB. Nevertheless, voice band codecs have many applications other than PCM, such as speech processing and encryption. They also dominate the more demanding audio markets, from FM stereo to DVD audio with total harmonic distortion plus noise (THD + N) requirements from 60 dB to greater than 100 dB, and sampling rates range from 48 kSPS to 192 kSPS.

Lower data rates

For lower data rate converter systems, Microchip’s MRF49XA can be used. It is a fully integrated, sub-GHz RF transceiver that can be easily interfaced with a variety of PIC microcontrollers through a 4-wire SPI, interrupt (IRO), and Reset to provide a wireless sensor network node for industrial automation applications.

The low-power single chip Frequency Shift Keying (FSK) baseband transceiver uses a Zero-IF architecture and PLL synthesizer and Low Noise Amplifier to provide a multi-channel and multi-band node.

Figure 3: The simplified functional block diagram of Microchip’s MRF49XA.

The MRF49XA is aimed at low-cost, low data rate applications under 256 kbps by providing a two-way and short range wireless link in the unlicensed 433 MHz, 868 MHz and 915 MHz frequency bands, and for applications looking for FCC, IC or ETSI certification in the ISM band.

The MRF49XA has a low phase noise and provides an excellent adjacent channel interference, Bit Error Rate (BER), and larger communication coverage along with higher output power. The PLL allows for the use of a low-accuracy, low-cost crystal. In order to minimize the total system cost, a communication link in most of the applications can be created using a low-cost, generic 10 MHz crystal, a bypass filter, and an affordable microcontroller. The MRF49XA also provides a clock signal for the microcontroller and avoids the need for a second crystal on the circuit board.

The MRF49XA communicates with the host microcontroller through a 4-wire SPI port as a slave device. An SPI compatible serial interface lets the user select, command and monitor the status of the MRF49XA through the host microcontroller. All registers consist of a command code, followed by a varying number of parameter or data bits. As the device uses word writes, the CS pin should be pulled low for 16 bits. Data bits on the SDI pin are shifted into the device upon the rising edge of the clock on the SCK pin whenever the CS pin is low.

Figure 4: The interface between a PIC microcontroller that takes the data from the sensor and MRF49XA.

The maximum clock frequency for the SPI bus is 20 MHz and the MRF49XA supports SPI mode 0,0. This requires the SCK to remain Idle in a low state, and the CS pin must be held low to enable communication between the host microcontroller and the MRF49XA.

Data is received by the transceiver through the SDI pin and is clocked on the rising edge of SCK. The transceiver sends out the data through the SDO pin and is clocked out on the falling edge of SCK. The Most Significant Bit (MSB) is sent first (e.g., bit 15- for a 16-bit command) in any data.

Higher data rates

For higher data rates, the EM351 from Silicon Labs is a fully integrated System-on-Chip that integrates a 2.4 GHz, IEEE 802.15.4-2003-compliant ZigBee transceiver, a 32-bit ARM Cortex™-M3 microprocessor, Flash and RAM memory, and some key peripherals.

The transceiver uses an efficient architecture that exceeds the dynamic range requirements of the IEEE 802.15.4-2003 standard by over 15 dB. This allows longer range, higher data rates, or lower power operation for the same range and data rate. The integrated receive channel filtering allows for robust coexistence with other communication standards in the 2.4 GHz spectrum, such as IEEE 802.11-2007, Wi-Fi, and Bluetooth. The integrated regulator, VCO, loop filter, and power amplifier keep the external component count and the optional high performance radio mode, or boost mode, is software-selectable to boost the dynamic range.

The integrated Cortex™-M3 microprocessor is highly optimized for high performance, low power consumption, and efficient memory utilization. Including an integrated MPU, it supports two different modes of operation – privileged mode and user mode. This architecture could allow for separation of the networking stack from the application code, and prevents unwanted modification of restricted areas of memory and registers resulting in increased stability and reliability of deployed solutions.

The EM351 has 128 kB of embedded flash memory and 12 kB of integrated RAM for data and program storage. The software uses an effective wear-leveling algorithm that optimizes the lifetime of the embedded flash.

Figure 5: Silicon Labs’ EM351 ZigBee system-on-chip.

To maintain the strict timing requirements imposed by the ZigBee and IEEE 802.15.4-2003 standards, the EM351 integrates a number of MAC functions, AES128 encryption accelerator, and automatic CRC handling into the hardware. The MAC hardware handles automatic ACK transmission and reception, automatic back-off delay, and clear channel assessment for transmission, as well as automatic filtering of received packets. The Packet Trace Interface is also integrated with the MAC, allowing complete, non-intrusive capture of all packets to and from the EM351 with development tools.

The EM351 offers a number of advanced power management features that enable long battery life. A high frequency internal RC oscillator allows the processor core to begin code execution quickly upon waking, and deep sleep modes are available with less than 1 µA power consumption while retaining RAM contents.

Data can be provided to the chip through a number of interfaces. The EM351 supports UART, SPI, TWI, ADC, and general-purpose timers, as well as up to 24 GPIOs that can also be used to take the digital output from the data converter to simplify the system design.


The design of a wireless node in an industrial automation application and the choice of components is very much dependent on the data acquisition architecture and data converters. Successive approximation converters can give a reliable, single shot reading that can be packetized and transmitted over the network when required, providing a low power, low cost implementation. Multiple sensors can be multiplexed into one data converter to link to one node, with the duty cycle and center frequency matched to the bandwidth of the sensor data. An 8-bit microcontroller and low cost transceiver can provide a cost effective low data rate wireless capability.

Sigma delta designs can provide a stream of high-resolution data from a sensor subsystem, making the most of the radio bandwidth and adding inherent protection against 50 Hz and 60 Hz noise from the industrial environment. A 32-bit microcontroller integrated with an optimized 2.4 GHz transceiver can provide a highly effective wireless interface that also reduces the interference of other wireless protocols in the same band.