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MCUs are key elements in many embedded sub-system designs, but often additional capabilities are required to implement the necessary system functions. Perhaps one of the most constrained elements in MCU-based designs is on-chip memory. A growing number of applications require more system memory than an MCU has available. In particular, advanced human-machine interface (HMI) designs can require a significant amount of read-only image and audio information not easily stored in MCU on-chip Flash memory. Additionally, a growing number of applications find on-chip RAM overly constraining for advanced communications channels that need significant data buffering and storage.
This article will quickly review some of the external memory interfaces available on modern MCUs. This will help a designer more efficiently implement MCU-based systems that require additional external storage—either as NVM Flash or volatile SRAM/DRAM.
External memory interfaces to SDRAM
Perhaps the most obvious external memory interface needed to extend storage capability is for large working SRAM. Typically, MCUs have a relatively small amount of on-chip SRAM and often an application will require more working memory than is available on-chip. Advanced user interfaces, for example, may require a significant amount of buffer memory for processing graphical user interfaces (GUIs) and creating video or audio prompts. Often, compression techniques are used when these data files are stored or transmitted to reduce local storage requirements or system bandwidth requirements. This means that a significant amount of working storage may be needed to decompress these files. Often, too, large working memories are needed in communications application or in digital-signal processing applications as buffer storage.
Many MCUs provide external-memory interface controllers with special circuits for controlling external SDRAM devices. An example MCU that highlights the key hardware elements used in supporting SDRAM interfaces is the NXP LPC1787 MCU. The external-memory controller peripheral, shown in Figure 1, has several programmable delay elements that are used to adjust the timing of key interface signals used in key SDRAM signals. For example, delay values for the two potential SDRAM clocks (CLKOUT1 and CLKOUT2) can be adjusted to position the transitions as required by the memory. Furthermore, another programmable delay adjusts the time at which the data read from the memory is sampled. Such timing adjustments, and their range and precision are critical in simplifying the memory interface, board layout, and the associated signal-timing checks.
The NXP LPC1787 external-memory interface also includes several other important hardware features that make external SDRAM interfaces more efficient. For example, the data buffers shown at the top of the block diagram can be used as read buffers, write buffers, or in combination. As write buffers they allow transactions to be grouped to minimize the number of external write operations, improving system bandwidth and reducing power dissipation. As read buffers they act as local data copies so further accesses to the same location can use the on-chip buffer version. This reduces the number of external read operations improving system bandwidth and reducing power dissipation.
Note that the NXP memory controller also supports static-memory interfaces for RAM, ROM, and Flash. This is a typical approach used in most modern MCU memory-controller peripherals since much of the hardware is common between both applications and often the applications do not need both types of memory simultaneously.
Configuring external memory
Often external memory is used for multiple purposes—it’s not viewed by the application as a monolithic “chunk” of storage. A method for configuring off-chip memory blocks to simplify memory access is helpful in simplifying application coding. One example of such a technique is used by the Silicon Labs C8051F70x/71x MCU family. In this MCU external memory is accessed using a special MOVX instruction. To make it easy to combine accesses to on-chip and off-chip memory, a portion of the on-chip memory can be mapped into the external-memory space. Figure 2 shows the four configuration modes available to map internal and external memory into the external-memory address space. In mode 1, shown on the far left of Figure 2, internal XRAM is mapped into the full external-memory space, with addresses “wrapping” when the on-chip XRAM memory address exceeds the amount of memory on-chip. This can be a useful mode when bringing the chip out of reset to avoid start-up issues with uninitialized external memory. Once the memory interface is successfully configured and tested the external memory space can be enabled. This mode is also available if external memory is not used.
In modes 2 and 3, the second and third from the left in Figure 2, the address space is split between on-chip and off-chip accesses. In mode 2, the bank select is not used to drive the higher order address bits onto the address bus; the user has control over these address values to provide additional flexibility. In mode 3, the on-chip bank address is automatically used to drive the external address bus, providing a simpler but less flexible approach. In mode 4, at the far right in Figure 2, off-chip memory is fully mapped to the external-address space. This makes it possible to access external data that might be inaccessible in the other address modes to fully utilize the available memory. If your application has several distinct types of external memory requirements—code, data buffers, translation tables, or audio/video processing it can simplify the design to use an external-memory controller with address-mapping and block-access features.
External-memory interface flexibility
In some applications it can be critical for the MCU external-memory interface to support multiple memory types while minimizing device pin count. A common combination is both Flash, for program storage, and SRAM, for use as working memory. If multiple memory interfaces are used on the MCU this can add 20 or more pins to the package, increasing cost, power dissipation, and board-space requirements. Some MCUs provide additional flexibility in the external-memory controller that can easily adapt to a variety of memory devices. For example, the popular Microchip PIC18F MCU family provides a flexible memory interface that can be extended to multiple device types. Figure 3 shows one approach to interface both a standard Flash memory and a standard SRAM with a single external bus. In this case a few external components (two 373 latches and a 138 decoder) are used to minimize the number of pins used on the MCU. (A simpler implementation is also possible for an 8-bit interface with only a single 373 latch required). External memory interfaces with this level of flexibility allow the “saved” IOs to be used for other functions, maximizing pin efficiency, one of the most important elements in MCU-based designs.
Interface timing flexibility
In addition to IO interconnect flexibility, external interfaces typically require some flexibility in timing. For example, wait states may need to be inserted if the memory is slower than the MCU clock cycle. Ideally, different external-memory blocks could be assigned different wait-state characteristics. This capability is even more important when the external interface can be used not only for standard memories but for memory mapper peripherals, such as liquid-crystal displays, analog-to-digital converters, and digital-to-analog converters. The Atmel ATmega MCU family can assign two different wait-state values to the external-memory space. As illustrated in Figure 4 below, memory configuration A allows external memory to be divided into two sectors—the upper sector and the lower sector. Sector size can have one of eight different values, adjusting the dividing line between the upper segment and the lower segment in 0x2000 increments from 0x2000 to 0xE000.
Dividing the external-memory space into two sectors makes it easy to group devices with larger wait-state values together and devices with smaller wait-state values together. Perhaps most importantly, if a zero wait-state memory is used for frequently accessed program data, a zero wait-state value can be used even if slower devices share the same memory bus. This minimizes MCU pin requirements while improving performance and saving power.
MCUs sometimes need to extend available on-chip memory by using an external-memory interface. Understanding the capabilities of these interfaces can reduce design time, lower cost, and improve system performance.
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